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參數(shù)資料
| 型號： | 82C862 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | FireLink USB Dual Controller Quad Port USB |
| 中文描述： | FireLink雙控制器的USB四口USB |
| 文件頁數(shù)： | 28/51頁 |
| 文件大?。?/td> | 321K |
| 代理商： | 82C862 |
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FireLink USB
82C862
912-2000-030
Revision: 1.0
Page 24
5.1.2 PCICFG 00h-FFh
7
6
5
4
3
2
1
0
PCICFG 00h
PCICFG 01h
Vendor Identification Register (RO)
Default = 45h
Default = 10h
PCICFG 02h
PCICFG 03h
Device Identification Register (RO)
Default = 61h
Default = C8h
PCICFG 04h
Command Register - Byte 0
Default = 00h
Wait cycle
control:
USB core does
not need to
insert a wait
state between
address and
data on the AD
lines. This bit is
always 0.
PERR#
(response)
detection
enable bit:
0 = PERR# not
asserted
1 = USB core
can assert
PERR# if it
is the
receiving
data agent
and detects
a data
parity error.
VGA palette
snooping:
This bit is
always 0.
Postable
memory write
command:
Not used when
USB core is a
master. This bit
is always 0.
Special Cycles:
USB core does
not run Special
Cycles on PCI.
This bit is
always 0.
USB core
can run
PCI master
cycles:
0 = Disable
1 = Enable
USB core
responds as
a target to
memory
cycles.
0 = Disable
1 = Enable
USB core
responds as
a target to I/O
cycles:
0 = Disable
1 = Enable
PCICFG 05h
Command Register - Byte 1
Default = 00h
Reserved: These bits are always 0.
Back-to-back
enable:
USB core only
acts as a
master to a
single device,
so this
functionality is
not needed.
This bit is
always 0.
SERR#
(response)
detection
enable bit:
0 = SERR# not
asserted
1 = USB core
asserts
SERR#
PCICFG 06h
Status Register - Byte 0
Default = 90h
Fast back-to-
back capability:
USB core
supports fast
back-to-back
transactions
when they are
not to same
agent. This bit
is always 1.
Reserved
Capabilities bit
(RO):
0=No PCI
Power
Management
1=PCI Power
Management
Available
See note.
Reserved
Note:
Bit [4] enables extended PCI capabilities. This bit =1 by default, enabling PCI power management capabilities. PCI power
management is enabled/disabled by a strap option, which can be overridden by writing PCICFG 4Dh[1]=0 to disable PCI PM, or writing
PCICFG 4Dh[1]=1 to enable PCI PM.
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