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參數(shù)資料
| 型號： | 84072xxx |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MICROCIRCUIT, DIGITAL, HIGH-SPEED CMOS, OCTAL TRANSPARENT D-TYPE LATCHES WITH THREE STATE OUTPUTS MONOLITIC SILICON |
| 中文描述： | 微電路，數(shù)字化，高速的CMOS，八路透明D類鎖存器與三態(tài)輸出MONOLITIC硅 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大小： | 166K |
| 代理商： | 84072XXX |
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
SIZE
A
84072
REVISION LEVEL
F
SHEET
8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Symbol
Test conditions 1/
-55
°
C
≤
T
C
≤
+125
°
C
unless otherwise specified
T
C
= +25
°
C
C
L
= 50 pF
See figure 4
3/
Test
Group A
subgroups
9
Limits
Unit
Propagation delay time,
output disable to any
output, OE to Qn
Min
Max
150
V
CC
= 2.0 V
V
CC
= 4.5 V
30
V
CC
= 6.0 V
26
ns
V
CC
= 2.0 V
225
V
CC
= 4.5 V
45
t
PHZ
,
t
PLZ
T
C
= -55
°
C and +125
°
C
C
L
= 50 pF
See figure 4
V
CC
= 6.0 V
10, 11
38
ns
V
CC
= 2.0 V
60
V
CC
= 4.5 V
12
T
C
= +25
°
C
C
L
= 50 pF
See figure 4
V
CC
= 6.0 V
9
10
ns
V
CC
= 2.0 V
90
V
CC
= 4.5 V
18
Transition time, output
rise and fall
t
THL
,
t
TLH
4/
T
C
= -55
°
C and +125
°
C
C
L
= 50 pF
See figure 4
V
CC
= 6.0 V
10, 11
15
ns
1/
2/
3/
4/
For a power supply of 5 V
±
10
%
, the worst case output voltages (V
OH
and V
OL
) occur for HC at 4.5 V. Thus, the
4.5 V values should be used when designing with this supply. Worst cases V
IH
and V
IL
occur at V
CC
= 5.5 V and
4.5 V respectively. (The V
IH
value at 5.5 V is 3.85 V.) The worst case leakage currents (I
IN
, I
CC
, and I
OZ
) occur for
CMOS at the higher voltage, so the 6.0 V values should be used. Power dissipation capacitance (C
PD
), typically
100 pF per latch, determines the no load dynamic power consumption, P
D
= C
PD
V
CC
dynamic current consumption, I
S
= C
PD
V
CC
f + I
CC
.
The V
IH
and V
IL
tests are not required because they are used as forcing functions for V
OH
or V
OL
.
AC testing at V
CC
= 2.0 V and V
CC
= 6.0 V shall be guaranteed, if not tested, to the specified limits in table I.
Transition time (t
TLH
, t
THL
), if not tested, shall be guaranteed to the specified limits in table I.
f + I
CC
V
CC
, and the no load
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