參數(shù)資料
型號(hào): 845PE
廠商: Intel Corp.
英文描述: 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述: 82845GE圖形和內(nèi)存控制器中樞(GMCH)和82845PE內(nèi)存控制器中樞(MCH)
文件頁(yè)數(shù): 45/176頁(yè)
文件大小: 2661K
代理商: 845PE
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Intel
82845GE/82845PE Datasheet
45
Register Description
3.4.2
CONFIG_DATA—Configuration Data Register
I/O Address:
Default Value:
Access:
Size:
CONFIG_DATA is a 32 bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents of
CONFIG_ADDRESS.
0CFCh
00000000h
Read/Write
32 bits
Bit
Description
31
Configuration Enable (CFGE).
1 = Enable.
0 = Disable.
30:24
Reserved.
These bits are read only and have a value of 0.
23:16
Bus Number.
When the Bus Number is programmed to 00h the target of the Configuration Cycle is
a hub interface agent ((G)MCH, ICH4, etc.). The Configuration Cycle is forwarded to the hub
interface if the Bus Number is programmed to 00h and the (G)MCH is not the target.
If the Bus Number is non-zero and matches the value programmed into the Secondary Bus Number
Register of Device 1, a Type 0 PCI configuration cycle will be generated on AGP/PCI_B.
If the Bus Number is non-zero, greater than the value in the Secondary Bus Number register of
Device 1 and less than or equal to the value programmed into the Subordinate Bus Number Register
of Device 1, a Type 1 PCI configuration cycle is generated on AGP/PCI_B.
If the Bus Number is non-zero, and does not fall within the ranges enumerated by Device 1’s
Secondary Bus Number or Subordinate Bus Number Register, then a HI Type 1 configuration Cycle
is generated.
15:11
Device Number.
This field selects one agent on the PCI bus selected by the Bus Number. When the
Bus Number field is “00” the (G)MCH decodes the Device Number field. The (G)MCH is always
Device Number 0 for the Host-HI bridge entity, Device Number 1 for the Host-PCI_B/AGP entity, and
device 2 for the integrated graphics device. Therefore, when the Bus Number =0 and the Device
Number equals 0,1 or 2, the internal (G)MCH devices are selected.
If the Bus Number is non-zero and matches the value programmed into the Device#1 Secondary
Bus Number Register, a Type 0 PCI configuration cycle will be generated on AGP/PCI_B. The
Device Number field is decoded and the (G)MCH asserts one and only one GADxx signal as an
IDSEL. GAD16 is asserted to access Device 0, GAD17 for Device 1 and so forth up to Device 15 for
which will assert AD31. All device numbers higher than #15 cause a type 0 configuration access with
no IDSEL asserted, which will result in a Master Abort reported in the (G)MCH’s “virtual” PCI-to-PCI
bridge registers.
For Bus Numbers resulting in AGP/PCI_B Type 1 Configuration cycles the Device Number is
propagated as GAD[15:11].
10:8
Function Number.
This field is mapped to GAD[10:8] during AGP/PCI_B Configuration cycles and
A[10:8] during HI configuration cycles. This allows the configuration registers of a particular function
in a multi-function device to be accessed. The (G)MCH ignores configuration cycles to its internal
Devices if the function number is not equal to 0.
7:2
Register Number.
This field selects one register within a particular Bus, Device, and Function as
specified by the other fields in the Configuration Address Register. This field is mapped to GAD[7:2]
during AGP/PCI_B Configuration cycles and A[7:2] during HI Configuration cycles.
1:0
Reserved.
Bit
Description
31:0
Configuration Data Window (CDW).
If bit 31 of CONFIG_ADDRESS is 1 any I/O access that to
the CONFIG_DATA register will be mapped to configuration space using the contents of
CONFIG_ADDRESS.
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