參數(shù)資料
型號： 845PE
廠商： Intel Corp.
英文描述： 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述： 82845GE圖形和內(nèi)存控制器中樞（GMCH）和82845PE內(nèi)存控制器中樞（MCH）
文件頁數(shù)： 49/176頁
文件大?。?/td> 2661K
代理商： 845PE
Intel
82845GE/82845PE Datasheet
49
Register Description
3.5.1.3
PCICMD
—
PCI Command Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
04–05h
0006h
RO, R/W
16 bits
Since (G)MCH Device 0 does not physically reside on PCI_A, many of the bits are not
implemented.
Bit
Description
15:10
Reserved.
9
Fast Back-to-Back Enable (FB2B)—RO.
Hardwired to 0. This bit controls whether or not the master
can do fast back-to-back write. Since Device 0 is strictly a target, this bit is not implemented.
8
SERR Enable (SERRE)—R/W.
This bit is a global enable bit for Device 0 SERR messaging. The
(G)MCH does not have an SERR signal. The (G)MCH communicates the SERR condition by
sending an SERR message over HI to the Intel
ICH4.
0 = Disable. The (G)MCH does not generate the SERR message for Device 0.
1 = Enable. (G)MCH is enabled to generate SERR messages over the hub interface for specific
Device 0 error conditions that are individually enabled in the ERRCMD register. The error status
is reported in the ERRSTS and PCISTS registers.
NOTE:
This bit only controls SERR messaging for the Device 0. Devices 1has its own SERRE bits
to control error reporting for error conditions occurring on their respective devices. The
control bits are used in a logical OR manner to enable the SERR HI message mechanism.
7
Address/Data Stepping Enable (ADSTEP)—RO.
Hardwired to 0. Not implemented.
6
Parity Error Enable (PERRE)—RO.
Hardwired to 0. PERR# is not implemented by the (G)MCH.
5
VGA Palette Snoop Enable (VGASNOOP)—RO.
Hardwired to 0. Not implemented.
4
Memory Write and Invalidate Enable (MWIE)—RO.
Hardwired to 0. The (G)MCH will never issue
memory write and invalidate commands.
3
Special Cycle Enable (SCE)—RO.
Hardwired to 0. The (G)MCH does not implement this bit.
2
Bus Master Enable (BME)—RO.
Hardwired to 1. The (G)MCH is always enabled as a master on the
hub interface.
1
Memory Access Enable (MAE)—RO.
Hardwired to 1. Not implemented. The (G)MCH always
allows access to main memory.
0
I/O Access Enable (IOAE)—RO.
Hardwired to 0. Not implemented.
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