參數(shù)資料
型號： 845PE
廠商： Intel Corp.
英文描述： 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述： 82845GE圖形和內(nèi)存控制器中樞（GMCH）和82845PE內(nèi)存控制器中樞（MCH）
文件頁數(shù)： 85/176頁
文件大?。?/td> 2661K
代理商： 845PE
Intel
82845GE/82845PE Datasheet
85
Register Description
3.5.2.19
PMBASE1—Prefetchable Memory Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
24–25h
FFF0h
R/W
16 bits
This register controls the processor to PCI_B prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE
≤
address
≤
PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeros
when read. This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1-MB boundary.
3.5.2.20
PMLIMIT1—Prefetchable Memory Limit Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
26–27h
0000h
RO, R/W
16 bits
This register controls the processor to PCI_B prefetchable memory accesses routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE
≤
address
≤
PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits
A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return zeroes
when read. This register must be initialized by the configuration software. For the purpose of
address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1-MB aligned memory block. Note that prefetchable
memory range is supported to allow segregation by the configuration software between the
memory ranges that must be defined as UC and the ones that can be designated as a USWC
(i.e, prefetchable) from the processor perspective.
Bit
Description
15:4
Prefetchable Memory Address Base (PMBASE).
This field corresponds to A[31:20] of the lower
limit of the address range passed by bridge Device 1 across AGP/PCI_B.
3:0
Reserved.
Bit
Description
15:4
Prefetchable Memory Address Limit (PMLIMIT).
This field corresponds to A[31:20] of the upper
limit of the address range passed by bridge Device 1 across AGP/PCI_B.
3:0
Reserved.
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