參數(shù)資料
型號: 845PE
廠商: Intel Corp.
英文描述: 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
中文描述: 82845GE圖形和內(nèi)存控制器中樞(GMCH)和82845PE內(nèi)存控制器中樞(MCH)
文件頁數(shù): 87/176頁
文件大?。?/td> 2661K
代理商: 845PE
Intel
82845GE/82845PE Datasheet
87
Register Description
The bit field definitions for VGAEN and MDAP are detailed in
Table 3-4
.
3.5.2.22
ERRCMD1—Error Command Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
40h
00h
R/W
8 bits
Table 3-4. VGAEN and MDAP Bit Definitions
VGAEN
MDAP
Description
0
0
All References to MDA and VGA space are routed to hub interface.
0
1
Illegal combination
1
0
All VGA references are routed to this bus. MDA references are routed to the hub
interface.
1
1
All VGA references are routed to this bus. MDA references are routed to hub interface.
Bit
Description
7:1
Reserved.
0
SERR on Receiving Target Abort (SERTA).
SERR messaging for Device 1 is globally enabled in
the PCICMD1 register.
0 = Disable. The (G)MCH does not assert an SERR message upon receipt of a target abort on
PCI_B.
1 = Enable. The (G)MCH generates an SERR message over the hub interface upon receiving a
target abort on PCI_B.
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