參數(shù)資料
型號: 853S011BGILFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, PDSO8
封裝: 3 X 3 MM, 0.97 MM HEIGHT, ROHS COMPLIANT, MO-187, TSSOP-8
文件頁數(shù): 18/20頁
文件大?。?/td> 825K
代理商: 853S011BGILFT
ICS853S011BGI REVISION A MAY 12, 2010
7
2010 Integrated Device Technology, Inc.
ICS853S011BI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.026ps (typical)
SSB
Phase
Nois
e
dB
c/H
z
Offset from Carrier Frequency (Hz)
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