參數(shù)資料
型號: 853S011BGILFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, PDSO8
封裝: 3 X 3 MM, 0.97 MM HEIGHT, ROHS COMPLIANT, MO-187, TSSOP-8
文件頁數(shù): 3/20頁
文件大?。?/td> 825K
代理商: 853S011BGILFT
ICS853S011BGI REVISION A MAY 12, 2010
11
2010 Integrated Device Technology, Inc.
ICS853S011BI Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface examples
for the PCLK/nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
Figure 2A. PCLK/nPCLK Input
Driven by a CML Driver
Figure 2C. PCLK/nPCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2E. PCLK/nPCLK Input
Driven by an SSTL Driver
Figure 2B. PCLK/nPCLK Input
Driven by a Built-In Pullup CML Driver
Figure 2D. PCLK/nPCLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
Figure 2F. PCLK/nPCLK Input Driven by
a 3.3V LVDS Driver
PCLK
nPCLK
LVPECL
Input
CML
3.3V
Zo = 50
Zo = 50
3.3V
R1
50
R2
50
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50
Zo = 50
PCLK
nPCLK
3.3V
LVPECL
Input
PCLK
nPCLK
LVPECL
Input
SSTL
2.5V
Zo = 60
Zo = 60
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
3.3V
R1
100
CML Built-In Pullup
PCLK
nPCLK
3.3V
LVPECL
Input
Zo = 50
Zo = 50
R1
50
R2
50
R5
100
- 200
R6
100
- 200
PCLK
VBB
nPCLK
3.3V LVPECL
3.3V
Zo = 50
Zo = 50
3.3V
LVPECL
Input
C1
C2
PCLK
nPCLK
VBB
3.3V
LVPECL
Input
R1
1k
R2
1k
3.3V
Zo = 50
Zo = 50
C1
C2
R5
100
LVDS
C3
0.1F
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