參數(shù)資料
型號: 934052190118
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: 55 A, 30 V, 0.018 ohm, N-CHANNEL, Si, POWER, MOSFET
文件頁數(shù): 1/10頁
文件大小: 85K
代理商: 934052190118
Philips Semiconductors
Product specification
TrenchMOS
transistor
PHB55N03T
Standard level FET
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
standard level field-effect power
transistor in a plastic envelope
V
DS
Drain-source voltage
30
V
suitable for surface mounting using
I
D
Drain current (DC)
55
A
’trench’ technology. The device
P
tot
Total power dissipation
103
W
features very low on-state resistance
T
j
Junction temperature
175
C
and has integral zener diodes giving
R
DS(ON)
Drain-source on-state
18
m
ESD protection up to 2kV. It is
resistance
V
GS = 10 V
intended
for
use
in
DC-DC
converters and general purpose
switching applications.
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
mb
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
DS
Drain-source voltage
-
30
V
DGR
Drain-gate voltage
R
GS = 20 k
-30
V
±V
GS
Gate-source voltage
-
20
V
I
D
Drain current (DC)
T
mb = 25 C
-
55
A
I
D
Drain current (DC)
T
mb = 100 C
-
38
A
I
DM
Drain current (pulse peak value)
T
mb = 25 C
-
220
A
P
tot
Total power dissipation
T
mb = 25 C
-
103
W
T
stg, Tj
Storage & operating temperature
-
- 55
175
C
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
R
th j-mb
Thermal resistance junction to
-
1.45
K/W
mounting base
R
th j-a
Thermal resistance junction to
minimum footprint, FR4
50
-
K/W
ambient
board
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
C
Electrostatic discharge capacitor
Human body model
-
2
kV
voltage, all pins
(100 pF, 1.5 k
)
d
g
s
13
mb
2
December 1997
1
Rev 1.200
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