參數(shù)資料
型號(hào)： 935185240518
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PDSO20
封裝： PLASTIC, SOT-266, SSOP-20
文件頁(yè)數(shù)： 5/30頁(yè)
文件大?。?/td> 251K
代理商： 935185240518
1997 Feb 27
13
Philips Semiconductors
Product specication
Power amplier controller for GSM and
PCN systems
PCF5075
6.6.1
Vk BITS
The Vk bits control the kick voltage in 64 steps of 4.8 mV per step.
6.6.2
Vh BITS
The Vh bits control the home position voltage in 64 steps of 32 mV per step.
6.6.3
PL BITS
The PL bits control the ramp-up top level voltage (equal to power level) in 256 steps of 11.7 mV per step.
7
LIMITING VALUES
VDD =VDDD =VDDA; VSS =VSSD =VSSA; in accordance with the Absolute Maximum Rating System (IEC 134).
8
OPERATING CHARACTERISTICS
Tamb = 40 to 85 °C; VDD =VDDA =VDDD; unless otherwise specied.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
0.5
7.0
V
VI
DC input voltage on all pins
0.5
7.0
V
II
DC current into any signal pin
10
+10
mA
Ptot
total power dissipation
83
mW
Tstg
storage temperature
65
150
°C
Tamb
operating ambient temperature
40
85
°C
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Operational amplier (OP1)
VDD
supply voltage
2.7
5.5
V
BG
gain bandwidth
at
3dB
4
MHz
SR(p)
positive slew rate
0.3
V/
s
SR(n)
negative slew rate
0.3
V/
s
Operational ampliers (OP2 and OP4)
VDD
supply voltage
2.7
5.5
V
BG
gain bandwidth
at
3 dB; unity gain;
CL = 120 pF; note 1
4
MHz
CMRR
common mode rejection ratio
45
dB
PSRR
power supply ripple rejection
for unity gain
50
dB
SR(p)
positive slew rate
for unity gain; note 2
4.5
V/
s
SR(n)
negative slew rate
for unity gain; note 2
4.5
V/
s
Vos
voltage offset
no load at output
7
0
+7
mV
CMil
common mode input low limit
± 5% tolerance; note 3
0.5
V
CMih
common mode input high
limit
± 5% tolerance;
notes 3 and 4
0.9VDD
V
Vo(min)
minimum output voltage
for unity gain
0.3
V
Vo(max)
maximum output voltage
for unity gain; note 4
0.85VDDD
V
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