參數(shù)資料
型號： 935185240518
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PDSO20
封裝： PLASTIC, SOT-266, SSOP-20
文件頁數(shù)： 8/30頁
文件大小： 251K
代理商： 935185240518
1997 Feb 27
16
Philips Semiconductors
Product specication
Power amplier controller for GSM and
PCN systems
PCF5075
10 TIMING CHARACTERISTICS
Tamb = 40 to +85 °C; VDD =VDDA =VDDD; VSS =VSSA =VSSD = 0 V; unless otherwise specied.
For timing see Fig.3; Tcy = 613 s.
Note
1. After rising edge of STROBE one more active CLK edge (LOW-to-HIGH transition) completes the transfer.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Controller timing
tqrs
negative pulse width on TRIG for quick restart recognition
0.077
0.769
s
tnoqrs
negative pulse width on TRIG for no quick restart recognition
1.0
s
td(TRIG-B)
delay from positive TRIG edge to point B = 13
6Tcy
1.0
s
td(B-C)
delay from point B to point C = 18Tcy
8.31
s
td(TRIG-E)
delay from negative TRIG edge to point E = 13
6Tcy
1.0
s
td(E-G)
delay from point E to point G = 38Tcy
17.54
s
Serial bus timing
SERIAL PROGRAMMING CLOCK (PIN 14)
tr
rise time
10
ns
tf
fall time
10
ns
Tcy
clock period
100
ns
ENABLE PROGRAMMING (PIN 13); note 1
tstart
strobe set-up time to rst clock edge
40
ns
tend
strobe hold time from rst clock edge
20
ns
REGISTER SERIAL INPUT DATA (PIN 15)
tsu
input data to CLK set-up time
20
ns
th
input data to CLK hold time
20
ns
handbook, full pagewidth
tend
tstart
tend
th
tsu
Tcy
Ladrs
CLK
Data
Strobe
MSB
MBE730
Fig.7 Serial bus timing diagram.
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935185540112 ABT SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20
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