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參數(shù)資料
| 型號(hào)： | 935260699551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁數(shù)： | 58/148頁 |
| 文件大?。?/td> | 692K |
| 代理商： | 935260699551 |
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1998 Apr 09
17
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7
FUNCTIONAL DESCRIPTION
This chapter provides information about the features
realized with this device. First, a general, thus short,
description of the functionality is given. The following
sections deal with the single features in a detailed manner.
7.1
General
The Dual D1 (DD1) interface can be connected to digital
video decoder ICs such as the SAA7110 and SAA7111A,
digital video encoder such as the SAA7185B, video
compression CODECs or to a D1 compatible connector,
e.g. for interconnection to an external digital camera.
The interface supports bidirectional full duplex two channel
full D1 (CCIR 656), optionally with separate sync lines
H/V, pixel qualifier signal and double pixel clock I/O, up to
32 MHz. It also supports a 16-bit parallel ‘YUV bus’ for
interfacing to the SAA7110.
One of the two internal video processors of the SAA7146A
is the two-dimensional High Performance Scaler (HPS).
Phase accurate re-sampling by interpolation supports
independent horizontal up and downscaling. In the
horizontal direction the scaling process is performed in two
functional blocks: integer decimation by window averaging
(up to 65 tap), and phase linear interpolation (10 tap filter
for luminance, 6 tap filter for chrominance). The vertical
processing for downscaling either uses averaging over a
window (up to 65 tap) or linear interpolation (2 tap).
The scaling function can be used for random sized display
windowing, for horizontal upscaling (zoom) or for
conversion between various sample schemes such as
CCIR or SQP. Incorporated with the HPS function is
brightness, contrast and saturation control. Colour key
generation is also established. The output of the HPS can
be formatted in various RGB and YUV formats.
Additionally, this output can be dithered for low bit rate
formats. Packed formats as well as planar formats (YUV)
are supported.
A second video channel (YUV4:2:2 format) bypasses
the HPS and connects the real time video interface with
the PCI interface. This video bypass channel, using the
second video processor Binary Ratio Scaler (BRS), is
bidirectional and has means to convert from full size video
(50 or 60 Hz) to Common Interchange Format (CIF),
Quarter Common Interchange Format (QCIF) or Quarter
Quarter Common Interchange Format (QQCIF) and vice
versa (binary ratio 1, 2, 4, 8, 1
2, 14 and 18 only). Multiple
programmable VBI data and test signal regions can be
bypassed without processing during each field.
The bidirectional digital audio serial interface is based on
the I2S-bus standard, but supports flexible programming
for various data and timing formats.
Two independent interface circuits control audio data
streaming of up to 2
× 128-bit frame width (bidirectional or
simultaneous input/output). Five or more I2S devices such
as the SAA7360 and SAA7366 (ADC) and SAA7350 and
SAA7351 (DAC) can be connected gluelessly.
The peripheral data port [Data Expansion Bus Interface
(DEBI)] enables 8 or 16-bit parallel access for system
set-up and programming of peripheral multimedia devices
(behind SAA7146A), but is also highly capable to interface
compressed MPEG/JPEG data of peripheral ICs with the
PCI system. DEBI supports both Intel compatible (ISA-bus
like) and Motorola (68000 style) compatible handshaking
protocols with up to 23 Mbytes/s peak data rate. Besides
the parallel port, there is also an I2C-bus port to control
peripheral ICs such as single-chip decoders SAA7110 and
SAA7111A or as encoders such as SAA7185B and
SAA7187 or as audio ICs.
The PCI interface has master read and master write
capability. The video signal flows to and from the PCI and
is controlled by three video DMA channels with a total
FIFO capacity of 384 Dwords. The video DMA channel
definition supports the typical video data structure
(hierarchy) of pixels, lines, fields and frames. The audio
signal flow is controlled by four audio DMA channels, each
with 24 Dwords FIFO capacity. The DEBI port is
connected to the PCI by single instruction direct access
(immediate mode) and via a data DMA channel for
streaming data (block mode) with 32 Dwords FIFO
capacity. To improve PCI-bus efficiency, an arbiter
schedules the access to PCI-bus for all local DMA
channels.
The PCI interface of the SAA7146A supports virtual
memory addressing for operating systems running virtual
demand paging. The integrated Memory Management
Unit (MMU) translates linear addressing to physical
addresses using a page table inside the system memory
provided by the software driver. The MMU supports up to
4 Mbytes of virtual address space per DMA channel.
The SAA7146A can change its programming sets using a
Register Programming Sequencer (RPS) that works by
itself on a user defined program controlled by internally
supported real time events. The SAA7146A has two RPS
machines to optimize flow control of e.g. an MPEG
compressed data stream and real time video scaling
control. The RPS programming is defined by an instruction
list in the system main memory that consists of multiple
RPS commands.
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