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| 型號(hào)： | 935260699551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁(yè)數(shù)： | 70/148頁(yè) |
| 文件大?。?/td> | 692K |
| 代理商： | 935260699551 |
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1998 Apr 09
28
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.2.4
MEMORY MANAGEMENT UNIT (MMU)
7.2.4.1
Introduction
To perform DMA transfers, physically continuous memory
space is needed. However, operating systems such as
Microsoft Windows are working with virtual demand
paging, using a MMU to translate linear to physical
addresses. Memory allocation is performed in the linear
address space, resulting in fragmented memory in the
physical address space. There is no way to allocate large
buffers of physical, continuous memory, except reserving
it during system start-up. Thus decreasing the system
performance dramatically. To overcome this problem the
SAA7146A contains a Memory Management Unit (MMU)
as well. This MMU is able to handle memory fragmented
to 4 kbyte pages, similar to the scheme used by the Intel
8086 processor family. The MMU can be bypassed to
simplify transfers to non-paged memory such as the
graphics adapter’s frame buffer.
7.2.4.2
Memory allocation
The SAA7146A’s MMU requires a special scheme for
memory allocation. The following steps have to be
performed:
Allocation of n pages, each page being 4 kbytes of size,
aligned to a 4 kbyte boundary
Allocation of one extra page, to be used as page table
Initialization of the page table.
Allocation of pages is done in physical address space.
Operating systems implementing virtual memory provide
services to allocate and free these pages.
The page table is stored in a separate page. This limits the
linear address page to a size of 4 Mbytes and results in a
4 kbyte overhead. The page table is organized as an array
of n Dwords, with each entry giving the physical address of
one of the n pages of allocated memory. As pages are
aligned to 4 kbytes, the lower 12 bits of each entry are
fixed to zero.
7.2.4.3
Implementation
The SAA7146A has up to 8 DMA channels (3 video,
4 audio and 1 DEBI channel) for which the memory
mapping is done. Each of them provides the linear address
to (from) which it wants to send (read) data during the next
transfer. Their register sets contain a page table base
address (Pagexx) and a mapping enable bit (MExx).
If MExx is set, mapping is enabled.
The MMU checks for each channel whether its address
has been already translated. If translated, its request can
pass to the Internal Arbitration Control (INTAC) managing
the access to the PCI-bus. If not, the MMU starts a bus
transfer to the page table. The page table entry address
could be calculated from the channels PCI address and
the page table base address, as shown in Fig.6. The upper
20 bits of the PCI address are replaced by the upper
20 bits of the according page address to generate the
mapped PCI address.
If the PCI address crosses a 4 kbyte boundary during a
transfer, the MMU stops this transfer and suppresses its
request to the INTAC until it has renewed the page
address, which means replacing the upper 20 bits of the
current address. To reduce latency the SAA7146A will do
a pre-fetch, i.e. it will always try to load the next page
address in advance.
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