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參數(shù)資料
| 型號(hào)： | 935260699551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁(yè)數(shù)： | 85/148頁(yè) |
| 文件大?。?/td> | 692K |
| 代理商： | 935260699551 |
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1998 Apr 09
41
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.4.4.10
LDREG and STREG
The Load Register (LDREG) command has a variable
Dword count specified by the Block_length. It is at least
two Dwords long and at maximum 256 Dwords.
The LDREG command interprets the following Dwords as
data and writes it to the registers beginning at the specified
register address (D6 to D0).
The Store Register (STREG) command is a two Dword
command. It transfers the contents of the addressed
(D6 to D0) SAA7146A register into PCI memory that is
addressed by interpreting the contents of the next data
Dword as the 32-bit target base address.
To perform STREG by two different tasks, a kind of
arbitration with two semaphore signals is necessary.
The Block_length entry defines the number of data
Dwords to be processed by these commands. This
enables the access to multiple registers on following
addresses within a single RPS command. The value
specified must be at least one. If more than one Dword is
accessed the register address is incremented each cycle.
A value of zero is reserved and the command will be
interpreted as NOP.
The register address defines the target register address in
Dwords. If this address points to a non-existent register the
RPS_RE (read error) bit for the actual task will be set and
if enabled an interrupt will be generated. The command will
be ignored and the execution of RPS continues.
All reserved bits should be written as zeros and should be
ignored during read cycles.
Table 30 LDREG command format
Table 31 STREG command format
D31 to D28
D27 to D16
D15 to D8
D7
D6 to D0
1001
reserved
Block_length
reserved
register address
(register offset divided-by-4)
D31 to D28
D27 to D16
D15 to D8
D7
D6 to D0
1010
reserved
Block_length
reserved
register address
(register offset divided-by-4)
Fig.7 Possible solution employing two semaphore signals to perform STREG commands with two tasks.
handbook, halfpage
MHB048
TASK0
SET SIG3
. . .
SET SIG3
CLR SIG3
JUMP IF SIG2 = 0 TO
STREG
ADDRESS
SET SIG3
. . .
TASK1
SET SIG2
. . .
CLR SIG2
WAIT ON SIG3
STREG
ADDRESS
SET SIG2
. . .
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