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| 型號(hào)： | 935260699551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁(yè)數(shù)： | 64/148頁(yè) |
| 文件大小： | 692K |
| 代理商： | 935260699551 |
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1998 Apr 09
22
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 3
Video DMA control registers
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
00
BaseOdd1
31 to 0
RW
PCI base address for odd elds of the upper (or lower if pitch is
negative) left pixel of the transferred eld
04
BaseEven1
31 to 0
RW
PCI base address for even elds of the upper (or lower if pitch is
negative) left pixel of the transferred eld
08
ProtAddr1
31 to 2
RW
protection address
1 and 0
reserved
0C
Pitch1
31 to 0
RW
distance between the start addresses of two consecutive lines of a single
eld
10
Page1
31 to 12
RW
base address of the page table (see Section 7.2.4)
ME1
11
RW
mapping enable; this bit enables the MMU
10 to 8
reserved
Limit1
7 to 4
RW
interrupt limit; denes the size of the memory range, that raise an
interrupt, if its boundaries are passed
PV1
3
RW
protection violation handling
2
reserved
Swap1
RW
endian swapping of all Dwords passing the FIFO 1:
00 = no swap
01 = two bytes swap (3210 to 2301)
10 = four bytes swap (3210 to 0123)
11 = reserved
14
NumLines1
27 to 16
RW
Number of lines per eld; it denes the number of qualied lines to be
processed by the HPS per eld. This will cut off all the following input lines
at the HPS input.
NumBytes1
11 to 0
RW
Number of pixels per line; it denes the number of qualied pixels to be
processed by the HPS per line. This will cut off all the following pixels at
the HPS input.
18
BaseOdd2
31 to 0
RW
PCI base address for odd elds of the upper (or lower if top-down ip is
selected) left pixel of the transferred eld
1C
BaseEven2
31 to 0
RW
PCI base address for even elds of the upper (or lower if top-down ip is
selected) left pixel of the transferred eld
20
ProtAddr2
31 to 2
RW
protection address
1 and 0
reserved
24
Pitch2
31 to 0
RW
distance between the start addresses of two consecutive lines of a eld
28
Page2
31 to 12
RW
base address of the page table (see Section 7.2.4)
ME2
11
RW
mapping enable; this bit enables the MMU
10 to 8
reserved
Limit2
7 to 4
RW
interrupt limit; denes the size of the memory range, that raise an
interrupt, if its boundaries are passed
PV2
3
RW
protection violation handling
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