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參數(shù)資料
| 型號(hào)： | 935262451557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁(yè)數(shù)： | 79/144頁(yè) |
| 文件大小： | 592K |
| 代理商： | 935262451557 |
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2000 Mar 15
4
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
1.5
Digital I/O interfaces
Real-time signal port (R port), inclusive continuous
line-locked reference clock and real-time status
information supporting RTC level 3.1 (refer to external
document
“RTC Functional Specification” for details)
Bi-directional expansion port (X-port) with half duplex
functionality (D1), 8-bit YUV
– Output from decoder part, real-time and unscaled
– Input to scaler part, e.g. video from MPEG decoder
(extension to 16-bit possible)
Video image port (I-port) configurable for 8-bit data
(extension to 16-bit possible) in master mode (own
clock), or slave mode (external clock), with auxiliary
timing and hand shake signals
Discontinuous data streams supported
32-word × 4-byte FIFO register for video output data
28-word × 4-byte FIFO register for decoded VBI output
data
Scaled 4:2:2, 4:1:1, 4:2:0, 4:1:0 YUV output
Scaled 8-bit luminance only and raw CVBS data output
Sliced, decoded VBI-data output.
1.6
Miscellaneous
Power-on control
5 V tolerant digital inputs and I/O ports
Software controlled power saving standby modes
supported
Programming via serial I2C-bus, full read-back ability by
an external controller, bit rate up to 400 kbits/s
Boundary scan test circuit complies with the “IEEE Std.
1149.b1 - 1994”.
2
APPLICATIONS
Desktop video
Multimedia
Digital television
Image processing
Video phone applications.
3
GENERAL DESCRIPTION
The SAA7114H is a video capture device for applications
at the image port of VGA controllers.
The SAA7114H is a combination of a two-channel analog
preprocessing circuit including source selection,
anti-aliasing filter and ADC, an automatic clamp and gain
control, a Clock Generation Circuit (CGC), a digital
multi-standard decoder containing two-dimensional
chrominance/luminance separation by an adaptive comb
filter and a high performance scaler, including variable
horizontal and vertical up and down scaling and a
brightness, contrast and saturation control circuit.
It is a highly integrated circuit for desktop video
applications. The decoder is based on the principle of
line-locked clock decoding and is able to decode the colour
of PAL, SECAM and NTSC signals into ITU 601
compatible colour component values. The SAA7114H
accepts as analog inputs CVBS or S-video (Y/C) from
TV or VCR sources, including weak and distorted signals.
An expansion port (X-port) for digital video (bi-directional
half duplex, D1 compatible) is also supported to connect to
MPEG or video phone codec. At the so called image port
(I-port) the SAA7114H supports 8 or 16-bit wide output
data with auxiliary reference data for interfacing to VGA
controllers.
The target application for SAA7114H is to capture and
scale video images, to be provided as digital video stream
through the image port of a VGA controller, for display via
VGA’s frame buffer, or for capture to system memory.
In parallel SAA7114H incorporates also provisions for
capturing the serially coded data in the vertical blanking
interval (VBI-data). Two principal functions are available:
1. To capture raw video samples, after interpolation to
the required output data rate, via the scaler
2. A versatile data slicer (data recovery) unit.
SAA7114H incorporates also a field locked audio clock
generation. This function ensures that there is always the
same number of audio samples associated with a field, or
a set of fields. This prevents the loss of synchronization
between video and audio, during capture or playback.
The circuit is I2C-bus controlled (full write/read capability
for all programming registers, bit rate up to 400 kbits/s).
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