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參數(shù)資料
| 型號： | 935262451557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁數(shù)： | 94/144頁 |
| 文件大?。?/td> | 592K |
| 代理商： | 935262451557 |
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2000 Mar 15
53
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
8.5
Image port output formatter
(subaddresses 84H to 87H)
The output interface consists of a FIFO for video and for
sliced text data, an arbitration circuit, which controls the
mixed transfer of video and sliced text data over the I-port
and a decoding and multiplexing unit, which generates the
8 or 16-bit wide output data stream and the accompanied
reference and supporting information.
The clock for the output interface can be derived from an
internal clock, decoder, expansion port, or an externally
provided clock which is appropriate for e.g. VGA and frame
buffer. The clock can be up to 33 MHz. The scaler provides
the following video related timing reference events
(signals), which are available on pins as defined by
subaddresses 84H and 85H:
Output field ID
Start and end of vertical active video range,
Start and end of active video line
Data qualifier or gated clock
Actually activated programming page (if CONLH is
used)
Threshold controlled FIFO filling flags (empty, full, filled)
Sliced data marker.
The disconnected data stream at the scaler output is
accompanied by a data valid flag (or data qualifier), or is
transported via a gated clock. Clock cycles with invalid
data on the I-port data bus (including the HPD pins in
16-bit output mode) are marked with code 00H.
The output interface also arbitrates the transfer between
scaled video data and sliced text data over the I-port
output.
The bits VITX1 and VITX0 (subaddress 86H) are used to
control the arbitration.
As further operation the serialization of the internal 32-bit
Dwords to 8-bit or optional 16-bit output, as well as the
insertion of the extended ITU 656 codes (SAV/EAV for
video data, ANC or SAV/EAV codes for sliced text data)
are done here.
For handshake with the VGA controller, or other memory
or bus interface circuitry, programmable FIFO flags are
provided (see Section 8.5.2).
8.5.1
SCALER OUTPUT FORMATTER
(SUBADDRESSES 93H AND C3H)
The output formatter organizes the packing into the output
FIFO. The following formats are available: YUV 4:2:2,
YUV4:1:1, YUV4:2:0, YUV 4:1:0, Y only (e.g. for
raw samples). The formatting is controlled by
FSI[2:0]93H[2:0], FOI[1:0]93H[4:3] and FYSK[93H[5]].
The data formats are defined on Dwords, or multiples, and
are similar to the video formats as recommended for PCI
multimedia applications (compare SAA7146A), but planar
formats are not supported.
FSI[2:0] defines the horizontal packing of the data,
FOI[1:0] defines, how many Y only lines are expected,
before a Y/C line will be formatted. If FYSK is set to logic 0
preceding Y only lines will be skipped, and output will
always start with a Y/C line.
Additionally the output formatter limits the amplitude range
of the video data (controlled by ILLV[85H[5]]); see
Table 17.
Table 15 Byte stream for different output formats
Table 16 Explanation to Table 15
OUTPUT FORMAT
BYTE SEQUENCE FOR 8-BIT OUTPUT MODES
YUV4:2:2
CB0Y0
CR0Y1
CB2Y2
CR2Y3
CB4Y4
CR4Y5
CB6Y6
YUV4:1:1
CB0Y0
CR0Y1
CB4Y2
CR4
Y3Y4
Y5Y6
Y7
CB8Y8
Y only
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
NAME
EXPLANATION
CBn
U (B
Y) colour difference component, pixel number n = 0, 2, 4 to 718
Yn
Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719
CRn
V (R
Y) colour difference component, pixel number n = 0, 2, 4 to 718
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