參數(shù)資料
型號: 93722CFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 93722 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
封裝: 0.209 INCH, LEAD FREE, MO-150, SSOP-28
文件頁數(shù): 6/7頁
文件大小: 84K
代理商: 93722CFLF
IDTTM/ICSTM Low Cost DDR Phase Lock Loop Zero Delay Buffer
ICS93722
REV F 02/11/07
ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
MIN
MAX
MIN
MAX
A
-
2.00
-
.079
A1
0.05
-
.002
-
A2
1.65
1.85
.065
.073
b
0.22
0.38
.009
.015
c
0.09
0.25
.0035
.010
D
E
7.40
8.20
.291
.323
E1
5.00
5.60
.197
.220
e
L
0.55
0.95
.022
.037
N
α
VARIATIONS
MIN
MAX
MIN
MAX
28
9.90
10.50
.390
.413
MO-150 JEDEC
Doc.# 10-0033
6/1/00 Rev B
SYMBOL
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
0.65 BASIC
0.0256 BASIC
N
D mm.
D (inch)
SEE VARIATIONS
α
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
.10 (.004) C
c
L
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1
E
209 mil SSOP
Ordering Information
ICS93722yFLFT
Example:
Designation for tape and reel packaging
Annealed Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS XXXX y F LF T
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