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參數資料
| 型號： | 93722CFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 93722 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.209 INCH, LEAD FREE, MO-150, SSOP-28 |
| 文件頁數： | 4/7頁 |
| 文件大?。?/td> | 84K |
| 代理商： | 93722CFLF |
IDTTM/ICSTM Low Cost DDR Phase Lock Loop Zero Delay Buffer
ICS93722
REV F 02/11/07
ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Recommended Operating Condition (see note 1)
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Analog / Core Supply Voltage
VDD, AVDD
2.3
2.5
2.7
V
VIL
VDD/2 - 0.5V
V
VIH
VDD/2 + 0.5V
V
Inpu Duty Cycle
IDC
40
60
Input max jitter
ITCYC
500
ps
Input Voltage Level
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Clock Frequency
1
freqop
66
200
MHz
Input Clock Duty Cycle
1
dtin
40
60
%
Clock Stabilization
1
tSTAB
from VDD = 2.5V to 1% target
frequency
100
s
1. Guaranteed by design, not 100% tested in production.
Timing Requirements
TA = 0 - 70°C; Supply Voltage VDD = 2.5 V +/-0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
66 MHz
120
100 - 200 MHz
75
66 MHz
50
110
100 - 200 MHz
25
65
Phase Error
1
t(phase error)
CLK_INT to FB_INT
-150
50
150
ps
Output to output Skew
1
Tskew
VT = 50%
70
100
ps
Pulse Skew
1
Tskewp
100
ps
VT = 50%, 66 MHz to 100 MHz
49.5
50
50.5
VT = 50%, 101 MHz to 167 MHz
49
50
51
Single-ended 20 - 80 %
Load = 120
/ 12 pF
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting output.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formula: duty cycle = twH / tC, where the cycle time (tC) decreases as the frequency increases.
Absolute Jitter
1
Tjabs
ps
Cycle to cycle Jitter
1,2
Tcyc-cyc
ps
Duty Cycle (differential)
1,3
950
ps
%
DC
Rise Time, Fall Time
1
tR, tF
450
550
Switching Characteristics
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相關代理商/技術參數 |
參數描述 |
|---|---|
| 93722CFLFT | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 93723-31872 | 制造商:FCI 功能描述:SMALL OUTLINE DIMM 3.3V |
| 93723-31872T | 制造商:FCI 功能描述:SINGLE PART CARD EDGE CONN |
| 937-235 | 功能描述:支架與墊片 Plastic Spcr .235 in Nylon White RoHS:否 制造商:Schurter 類型:Transipillar Spacers 長度:16 m 螺紋大小:M4 外徑:10 mm 材料:Nylon with Steel 電鍍:Zinc |
| 93723-51872 | 制造商:FCI 功能描述:SMALL OUTLINE DIMM 5V |
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