參數(shù)資料
型號: 93722CFLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 93722 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 6 INVERTED OUTPUT(S), PDSO28
封裝: 0.209 INCH, LEAD FREE, MO-150, SSOP-28
文件頁數(shù): 2/7頁
文件大?。?/td> 84K
代理商: 93722CFLF
IDTTM/ICSTM Low Cost DDR Phase Lock Loop Zero Delay Buffer
ICS93722
REV F 02/11/07
ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Pin Description
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Byte 5: Output Control
(1= enable, 0 = disable)
Byte 6: Output Control
(1= enable, 0 = disable)
Note: PWD = Power Up Default
Bytes 0 to 4 are reserved power up default = 1.
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相關(guān)PDF資料
PDF描述
93725AF-T 93725 SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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93725AF 93725 SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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