參數(shù)資料
型號: 9S12KT256DGV1
英文描述: MC9S12KT256 Device User Guide
中文描述: MC9S12KT256設(shè)備用戶指南
文件頁數(shù): 100/126頁
文件大?。?/td> 7307K
代理商: 9S12KT256DGV1
Device User Guide — 9S12KT256DGV1/D V01.09
100
Freescale Semiconductor
Table A-15 3.3V ATD Conversion Performance
Conditions are shown in
Table A-4
unless otherwise noted
V
REF
= V
RH
- V
RL
= 3.328V. Resulting to one 8 bit count = 13mV and one 10 bit count = 3.25mV
f
ATDCLK
= 2.0MHz
Num C
Rating
For the following definitions see also
Figure A-2
.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
NOTES
:
1. These values include quantization error which is inherently 1/2 count for any A/D converter.
Symbol
Min
Typ
Max
Unit
1
P 10-Bit Resolution
LSB
3.25
mV
2
P 10-Bit Differential Nonlinearity
DNL
–1.5
1.5
Counts
3
P 10-Bit Integral Nonlinearity
INL
–3.5
±
1.5
3.5
Counts
4
P 10-Bit Absolute Error
1
NOTES
:
1. These values include the quantization error which is inherently 1/2 count for any A/D converter.
AE
-5
±
2.5
5
Counts
5
C 10-Bit Absolute Error at f
ATDCLK
= 4MHz
AE
±
7.0
Counts
6
P 8-Bit Resolution
LSB
13
mV
7
P 8-Bit Differential Nonlinearity
DNL
–0.5
0.5
Counts
8
P 8-Bit Integral Nonlinearity
INL
–1.5
±
0.1
1.5
Counts
9
P 8-Bit Absolute Error
(1)
AE
-2.0
±
1.5
2.0
Counts
DNL i
( )
V
i
------------------------
V
i
1
1LSB
1
=
INL n
DNL i
( )
i
1
=
n
V
n
1LSB
V
0
-------------------
n
=
=
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