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| 型號(hào)： | 9S12KT256DGV1 |
| 英文描述： | MC9S12KT256 Device User Guide |
| 中文描述： | MC9S12KT256設(shè)備用戶指南 |
| 文件頁(yè)數(shù)： | 98/126頁(yè) |
| 文件大?。?/td> | 7307K |
| 代理商： | 9S12KT256DGV1 |
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Device User Guide — 9S12KT256DGV1/D V01.09
98
Freescale Semiconductor
Table A-12 3.3V ATD Operating Characteristics
Conditions are shown in
Table A-4
unless otherwise noted; Supply Voltage 3.3V-10% <= V
DDA
<= 3.3V+10%
A.5.2 Factors influencing accuracy
Three factors - source resistance, source capacitance and current injection - have an influence on the
accuracy of the ATD.
A.5.2.1 Source Resistance:
Due to the input pin leakage current as specified in
Table A-6
and
Table A-7
in conjunction with the
source resistance there will be a voltage drop from the signal source to the ATD input. The maximum
source resistance R
S
specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage
current. If device or operating conditions are less than worst case or leakage-induced error is acceptable,
larger values of source resistance are allowed.
A.5.2.2 Source capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input
voltage
≤
1LSB, then the external filter capacitor, C
f
≥
1024 * (C
INS
- C
INN
).
A.5.2.3 Current injection
There are two cases to consider.
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
D
Reference Potential
Low
High
V
RL
V
RH
V
SSA
V
DDA
/2
3.0
V
DDA
/2
V
DDA
3.6
V
V
2
C Differential Reference Voltage
V
RH
-V
RL
f
ATDCLK
3.3
V
3
D ATD Clock Frequency
0.5
2.0
MHz
4
D
ATD 10-Bit Conversion Period
Clock Cycles
1
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
Conv, Time at 4.0MHz
2
ATD Clock f
ATDCLK
NOTES
:
1. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample
period of 16 ATD clocks.
2. Reduced accuracy see
Table A-14
and
Table A-15
.
N
CONV10
T
CONV10
T
CONV10
14
7
3.5
28
14
7
Cycles
μ
s
μ
s
5
D
ATD 8-Bit Conversion Period
Clock Cycles
(1)
Conv, Time at 2.0MHz ATD Clock f
ATDCLK
N
CONV8
T
CONV8
12
6
26
13
Cycles
μ
s
6
D Recovery Time (V
DDA
=3.3 Volts)
t
REC
I
REF
I
REF
20
μ
s
7
P
Reference Supply current (two ATD modules)
0.500
mA
8
P
Reference Supply current (one ATD module)
0.250
mA
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