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| 型號(hào)： | 9S12KT256DGV1 |
| 英文描述： | MC9S12KT256 Device User Guide |
| 中文描述： | MC9S12KT256設(shè)備用戶指南 |
| 文件頁(yè)數(shù)： | 105/126頁(yè) |
| 文件大?。?/td> | 7307K |
| 代理商： | 9S12KT256DGV1 |
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Device User Guide — 9S12KT256DGV1/D V01.09
105
Freescale Semiconductor
A.7 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.7.1 Startup
Table A-18
summarizes several startup characteristics explained in this section. Detailed description of
the startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-18 Startup Characteristics
A.7.1.1 POR
The release level V
PORR
and the assert level V
PORA
are derived from the V
DD
Supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
A.7.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.7.1.3 External Reset
When external reset is asserted for a time greater than PW
RSTL
the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.7.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
Conditions are shown in
Table A-4
unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
T POR release level
V
PORR
2.07
V
2
T POR assert level
V
PORA
0.97
V
3
D Reset input pulse width, minimum input time
PW
RSTL
2
t
osc
4
D Startup from Reset
n
RST
192
196
n
osc
5
D Interrupt pulse width, IRQ edge-sensitive mode
PW
IRQ
20
ns
6
D Wait recovery startup time
t
WRS
14
t
cyc
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