參數(shù)資料
型號： 9S12KT256DGV1
英文描述： MC9S12KT256 Device User Guide
中文描述： MC9S12KT256設(shè)備用戶指南
文件頁數(shù)： 59/126頁
文件大?。?/td> 7307K
代理商： 9S12KT256DGV1
Device User Guide — 9S12KT256DGV1/D V01.09
59
Freescale Semiconductor
Table 2-2 Power and Ground
PP3
KWP3
PWM3
SS1
VDDX
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERP/
PPSP
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
PERS/
PPSS
Up or
Down
Disabled
Port P I/O, Interrupt, PWM Channel 3,
SPI1 SS
Port P I/O, Interrupt, PWM Channel 2,
SPI1 SCK
Port P I/O, Interrupt, PWM Channel 1,
SPI1 MOSI
Port P I/O, Interrupt, PWM Channel 0,
SPI1 MISO
PP2
KWP2
PWM2
SCK1
VDDX
Disabled
PP1
KWP1
PWM1
MOSI1
VDDX
Disabled
PP0
KWP0
PWM0
MISO1
VDDX
Disabled
PS7
SS0
—
—
VDDX
Up
Port S I/O, SPI0 SS
PS6
SCK0
—
—
VDDX
Up
Port S I/O, SPI0 SCK
PS5
MOSI0
—
—
VDDX
Up
Port S I/O, SPI0 MOSI
PS4
MISO0
—
—
VDDX
Up
Port S I/O, SPI0 MISO
PS3
TXD1
—
—
VDDX
Up
Port S I/O, SCI1TXD
PS2
RXD1
—
—
VDDX
Up
Port S I/O, SCI1RXD
PS1
TXD0
—
—
VDDX
Up
Port S I/O, SCI0 TXD
PS0
RXD0
—
—
VDDX
Up
Port S I/O, SCI0 RXD
PT[7:0]
IOC[7:0]
—
—
VDDX
Disabled Port T I/O, Timer channels
NOTES
:
1. Only available on MC9S12KT256.
Mnemonic
Nominal
Voltage
Description
VDD1
VDD2
VSS1
VSS2
VDDR
VSSR
VDDX
VSSX
VDDA
2.5 V
Internal power and ground generated by internal regulator. These also
allow an external source to supply the core VDD/VSS voltages and
bypass the internal voltage regulator.
0V
3.3/5.0 V
0 V
3.3/5.0 V
0 V
3.3/5.0 V
External power and ground, supply to pin drivers and internal voltage
regulator.
External power and ground, supply to pin drivers.
Operating voltage and ground for the analog-to-digital converter and
the reference for the internal voltage regulator, allows the supply
voltage to the A/D to be bypassed independently.
Reference voltage high for the ATD converter.
Reference voltage low for the ATD converter.
VSSA
0 V
VRH
VRL
3.3/5.0 V
0 V
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Pin Name
Function 4
Powered
by
Internal Pull
Resistor
Description
CTRL
Reset
State
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