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參數(shù)資料
| 型號： | A28F010 |
| 廠商： | Intel Corp. |
| 英文描述： | 1024K (128K x 8) CMOS Flash Memory(1024K (128K x 8) CMOS閃速存儲器) |
| 中文描述： | 1024K（128K的× 8）的CMOS閃存（1024K（128K的× 8）的CMOS閃速存儲器） |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 284K |
| 代理商： | A28F010 |
A28F010
DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory ar-
rays. Intel provides two read-control inputs to ac-
commodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an ad-
dress-decoder output should drive chip-enable,
while the system’s read signal controls all flash-
memories and other parallel memories. This assures
that only enabled memory devices have active out-
puts, while deselected devices maintain the low
power standby condition.
Power Supply Decoupling
Flash memory power-switching characteristics re-
quire careful device decoupling. System designers
are interested in three supply current (I
CC
) issuesD
standby, active, and transient current peaks pro-
duced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1
m
F ceramic capacitor
connected between V
CC
and V
SS
, and between V
PP
and V
SS
.
Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7
m
F electrolytic capaci-
tor should be placed at the array’s power supply
connection, between V
CC
and V
SS
. The bulk capaci-
tor will overcome voltage slumps caused by printed-
circuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
V
PP
Trace on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V
PP
power sup-
ply trace. The V
PP
pin supplies the memory cell cur-
rent for programming. Use similar trace widths and
layout considerations given the V
CC
power bus. Ad-
equate V
PP
supply traces and decoupling will de-
crease V
PP
voltage spikes and overshoots.
Power Up/Down Protection
The 28F010 is designed to offer protection against
accidental erasure or programming, caused by spur-
ious system-level signals that may exist during pow-
er transitions. Also, with its control register architec-
ture, alteration of memory contents only occurs after
successful completion of the two-step command se-
quences. Power supply sequencing is not required.
Internal circuitry of the 28F010 ensures that the
command register architecture is reset to the read
mode on power up.
A system designer must guard against active writes
for V
CC
voltages above the V
LKO
when V
PP
is ac-
tive. Since both WE
Y
and CE
must be low for a
command write, driving either to V
IH
will prohibit
writes. The control register architecture provides an
added level of protection since alteration of memory
contents only occurs after successful completion of
the two-step command sequences.
28F010 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F010.
Table 4. 28F010 Typical Update
Power Dissipation
(4)
Operation
Power Dissipation
(Watt-Seconds)
Notes
Array Program/
Program Verify
0.171
1
Array Erase/
Erase Verify
0.136
2
One Complete
Cycle
0.478
3
NOTES:
1. Formula to calculate typical Program/Program Verify
Power
e
[
V
PP
(t
WHWH1
c
I
PP2
typical
a
t
WHGL
c
I
PP4
typical)
a
V
CC
c
Bytes
c
typical
Y
Prog Pulses (t
WHWH1
c
I
CC2
typi-
cal
a
t
WHGL
c
I
CC4
typical
]
.
2. Formula to calculate typical Erase/Erase Verify Power
e
[
V
PP
(V
PP3
typical
c
t
ERASE
typical
a
I
PP5
typical
c
t
WHGL
c
Y
Bytes)
]
a
[
V
CC
(I
CC3
typical
c
t
ERASE
typical
c
I
CC5
typical
c
t
WHGL
c
Y
Bytes)
]
.
3. One Complete Cycle
e
Array Preprogram
a
Array
Erase
a
Program.
4. ‘‘Typicals’’ are not guaranteed, but based on a limited
number of samples from production lots.
c
Y
Bytes
c
typical
Y
Prog Pulses
12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A28F200BR-B | 2-MBIT (256K x 8) Boot Block Flash Memory(2兆位 (128K x 16) 引導(dǎo)塊閃速存儲器) |
| A28F200BR-T | 2-MBIT (128K x 16) Boot Block Flash Memory(2兆位 (128K x 16) 引導(dǎo)塊閃速存儲器) |
| A28F200BX-B | 2-MBIT (256K x 8) Boot Block Flash Memory(2兆位 (128K x 16) 引導(dǎo)塊閃速存儲器) |
| A28F400BR-B | 4-MBIT (512K x8) Boot Block Flash Memory(4兆位(512K x8) 引導(dǎo)塊閃速存儲器) |
| A28F400BR-T | 4-MBIT (256K x16) Boot Block Flash Memory(4兆位 (256K x16)引導(dǎo)塊閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A28F200BR-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K X 16. 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BR-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K X 16. 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BR-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BR-T/B |
| A28F200BR-TB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K X 16, 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BX-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BX-B - 2-MBIT (128K x 16. 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
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