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參數(shù)資料
| 型號： | A28F010 |
| 廠商： | Intel Corp. |
| 英文描述： | 1024K (128K x 8) CMOS Flash Memory(1024K (128K x 8) CMOS閃速存儲器) |
| 中文描述： | 1024K（128K的× 8）的CMOS閃存（1024K（128K的× 8）的CMOS閃速存儲器） |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 284K |
| 代理商： | A28F010 |
A28F010
AC CHARACTERISTICSDWrite/Erase/Program Operations
(1, 3)
Versions
Notes
28F010-120
28F010-150
Unit
Symbol
Characteristic
Min
Max
Min
Max
t
AVAV
/t
WC
Write Cycle Time
120
150
ns
t
AVWL
/t
AS
Address Set-Up Time
0
0
ns
t
WLAX
/t
AH
Address Hold Time
2
60
60
ns
t
DVWH
/t
DS
Data Set-up Time
50
50
ns
t
WHDX
/t
DH
Data Hold Time
10
10
ns
t
WHGL
Write Recovery Time before Read
6
6
m
s
t
GHWL
Read Recovery Time before Write
0
0
m
s
t
ELWL
/t
CS
Chip Enable
Set-Up Time before Write
2
20
20
ns
t
WHEH
/t
CH
Chip Enable Hold Time
0
0
ns
t
WLWH
/t
WP
Write Pulse Width
(2)
2
80
80
ns
t
ELEH
Alternative Write
(2)
Pulse Width
2
80
80
ns
t
WHWL
/t
WPH
Write Pulse Width High
20
20
ns
t
WHWH1
Duration of Programming Operation
4
10
10
m
s
t
WHWH2
Duration of Erase Operation
4
9.5
9.5
ms
t
VPEL
V
PP
Set-Up
Time to Chip Enable Low
1.0
1.0
ms
NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Char-
acteristics for Read-Only Operations.
2. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold, and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
3. Rise/Fall time
s
10 ns.
4. The internal stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum speci-
fication.
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Notes
Limits
Unit
Comments
Min
Typ
Max
Chip Erase Time
1, 3, 4, 6
1
60
Sec
Excludes 00H Programming
Prior to Erasure
Chip Program Time
1, 2, 4
2
12.5
Sec
Excludes System-Level Overhead
Erase/Program Cycles
1, 5
1,000
100,000
Cycles
NOTES:
1. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples taken from production lots. Data taken at
T
e
25
§
C, V
PP
e
12.0V, V
CC
e
5.0V.
2. Minimum byte programming time excluding system overhead is 16
m
sec (10
m
sec program
a
6
m
sec write recovery),
while maximum is 400
m
sec/byte (16
m
sec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes 00H programming prior to erasure.
4. Excludes system-level overhead.
5. Refer to RR-60 ‘‘ETOX Flash Memory Reliability Data Summary’’ for typical cycling data and failure rate calculations.
6. Maximum erase specification is determined by algorithmic limit and accounts for cumulative effect of erasure at
T
e b
40
§
C, 1,000 cycles, V
PP
e
11.4V, V
CC
e
4.5V.
18
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A28F200BR-B | 2-MBIT (256K x 8) Boot Block Flash Memory(2兆位 (128K x 16) 引導塊閃速存儲器) |
| A28F200BR-T | 2-MBIT (128K x 16) Boot Block Flash Memory(2兆位 (128K x 16) 引導塊閃速存儲器) |
| A28F200BX-B | 2-MBIT (256K x 8) Boot Block Flash Memory(2兆位 (128K x 16) 引導塊閃速存儲器) |
| A28F400BR-B | 4-MBIT (512K x8) Boot Block Flash Memory(4兆位(512K x8) 引導塊閃速存儲器) |
| A28F400BR-T | 4-MBIT (256K x16) Boot Block Flash Memory(4兆位 (256K x16)引導塊閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A28F200BR-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K X 16. 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BR-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2-MBIT (128K X 16. 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BR-T/B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BR-T/B |
| A28F200BR-TB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K X 16, 256K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F200BX-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A28F200BX-B - 2-MBIT (128K x 16. 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY |
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