參數(shù)資料
型號(hào)： A40MX04-PLG44A
元件分類： FPGA
英文描述： FPGA, 6000 GATES, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 3/76頁(yè)
文件大?。?/td> 429K
代理商： A40MX04-PLG44A
MX Automotive Family FPGAs
v2.0
1-5
Antifuse Structures
An antifuse is a “normally open” structure as opposed to
the normally connected fuse structure used in PROMs or
PALs. The use of antifuses to implement a programmable
logic device results in highly testable structures as well as
efficient programming algorithms. The structure is
highly-testable
because
there
are
no
pre-existing
connections; therefore, temporary connections can be
made
using
pass
transistors.
These
temporary
connections can isolate individual antifuses to be
programmed and individual circuit structures to be
tested,
which
can
be
done
before
and
after
programming. For example, all metal tracks can be
tested for continuity and shorts between adjacent tracks,
and the functionality of all logic modules can be verified.
Clock Networks
The 40MX devices have one global clock distribution
network
(CLK).
Two
low-skew,
high-fanout
clock
distribution networks are provided in each 42MX device.
These networks are referred to as CLK0 and CLK1. Each
network has a clock module (CLKMOD) that selects the
source of the clock signal and may be driven as follows:
Externally from the CLKA pad
Externally from the CLKB pad
Internally from the CLKINTA input
Internally from the CLKINTB input
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
The user controls the clock module by selecting one of
two clock macros from the macro library. The macro
CLKBUF is used to connect one of the two external clock
pins to a clock network, and the macro CLKINT is used to
connect an internally-generated clock signal to a clock
network. Since both clock networks are identical, it does
not matter whether CLK0 or CLK1 is being used. The
clock input pads can also be used as normal I/Os,
bypassing the clock networks (Figure 1-8).
The A42MX36 device has four additional register control
resources, called quadrant clock networks (Figure 1-9 on
page 1-6). Each quadrant clock provides a local, high-
fanout resource to the contiguous logic modules within
its quadrant of the device. Quadrant clock signals can
originate from specific I/O pins or from the internal array
and can be used as a secondary register clock, register
clear, or output enable.
Test Circuitry
All MX automotive-grade
devices contain
probing
circuitry which test and debug a design once it is
programmed into a device. The test circuitry allows the
designer to probe any internal node during device
operation to aid in debugging a design.
IEEE Standard 1149.1 Boundary
Scan Testing (BST)
A42MX24 and A42MX36 devices contain IEEE Standard
1149.1 boundary scan test circuitry. IEEE Standard 1149.1
defines a four-pin Test Access Port (TAP) interface for
testing integrated circuits in a system. The A42MX24 and
A42MX36 devices provide the following BST pins: Test
Data In (TDI), Test Data Out (TDO), Test Clock (TCK), and
Test Mode Select (TMS). Devices are configured in a test
“chain” where BST data can be transmitted serially
between devices via TDO-to-TDI interconnections. The
TMS and TCK signals are shared among all devices in the
test chain so that all components operate in the same
state.
The 42MX family implements a subset of the IEEE
Standard 1149.1 BST instruction in addition to a private
instruction.
Refer
to
the
IEEE
Standard
1149.1
specification for detailed information regarding BST.
Boundary Scan Circuitry
The A42MX24 and A42MX36 boundary-scan circuitry
consists of a Test Access Port (TAP) controller, test
instruction register, a bypass register, and a boundary
scan register. Figure 1-10 on page 1-6 shows a block
diagram of the 42MX boundary scan circuitry.
Figure 1-8 42MX Clock Networks
CLKB
CLKA
From
Pads
Clock
Drivers
CLKMOD
CLKINB
CLKINA
S0
S1
Internal
Signal
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
相關(guān)PDF資料
PDF描述
A40MX04-PLG68A FPGA, 6000 GATES, PQCC68
A42MX36-BG272A FPGA, 54000 GATES, PBGA272
A42MX36-BGG272A FPGA, 54000 GATES, PBGA272
A42MX36-CQ208A FPGA, 54000 GATES, CQFP208
A42MX36-CQ256A FPGA, 54000 GATES, CQFP256
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX04-PLG44I 功能描述:IC FPGA MX SGL CHIP 6K 44-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-PLG44M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 44PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 34 I/O 44PLCC
A40MX04-PLG68 功能描述:IC FPGA 69I/O 68PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門(mén)數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28）
A40MX04-PLG68I 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-PLG68M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 68PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 57 I/O 68PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC
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