參數(shù)資料
型號: A40MX04-PLG44A
元件分類: FPGA
英文描述: FPGA, 6000 GATES, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 37/76頁
文件大?。?/td> 429K
代理商: A40MX04-PLG44A
MX Automotive Family FPGAs
1- 3 6
v2 .0
tIRD2
FO=2 Routing Delay
3.6
ns
tIRD3
FO=3 Routing Delay
4.0
ns
tIRD4
FO=4 Routing Delay
4.3
ns
tIRD8
FO=8 Routing Delay
6.0
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=486
4.6
5.1
ns
tCKL
Input HIGH to LOW
FO=32
FO=486
6.3
7.4
ns
tPWH
Minimum Pulse Width HIGH
FO=32
FO=486
3.8
4.1
ns
tPWL
Minimum Pulse Width
LOW
FO=32
FO=486
3.8
4.1
ns
tCKSW
Maximum Skew
FO=32
FO=486
0.9
ns
tSUEXT
Input Latch External Set-Up
FO=32
FO=486
0.0
ns
tHEXT
Input Latch External Hold
FO=32
FO=486
4.8
5.8
ns
tP
Minimum Period (1/fMAX)FO=32
FO=486
7.6
8.4
ns
fMAX
Maximum Datapath Frequency
FO=32
FO=486
180
165
MHz
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
4.2
ns
tDHL
Data-to-Pad LOW
4.9
ns
tENZH
Enable Pad Z to HIGH
4.5
ns
tENZL
Enable Pad Z to LOW
4.9
ns
tENHZ
Enable Pad HIGH to Z
8.9
ns
tENLZ
Enable Pad LOW to Z
8.3
ns
tGLH
G-to-Pad HIGH
5.1
ns
Table 1-9 A42MX24 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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