參數(shù)資料
型號(hào)： A40MX04-PLG44A
元件分類(lèi)： FPGA
英文描述： FPGA, 6000 GATES, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 43/76頁(yè)
文件大?。?/td> 429K
代理商： A40MX04-PLG44A
MX Automotive Family FPGAs
1- 4 2
v2 .0
Pin Descriptions
CLK, CLKA,B, I/O
Global Clock (Input)
TTL clock inputs for clock distribution networks. The
clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK, I/O
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Ground (Input)
Input LOW supply voltage.
I/O
Input/Output (Input, Output)
Input, output, tri-state, or bi-directional buffer. Input
and output levels are compatible with standard TTL and
CMOS specifications. Unused I/O pins are automatically
driven LOW by the Designer Series software.
MODE
Mode (Input)
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). To provide verification capability, the MODE
pin should be held HIGH. To facilitate this, the MODE pin
should be tied to GND through a 10K
resistor so that
the MODE pin can be pulled HIGH when required.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, PRB, I/O
Probe
The pins are used for real-time diagnostic output of any
signal path within the device. Each pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRA and
PRB are accessible when the MODE pin is HIGH. These
pins function as I/Os when the MODE pin is LOW.
QCLKA,B,C,D, I/O
Quadrant Clock (Input/Output)
Quadrant clock inputs. When not used as a register
control signal, these pins can function as general-
purpose I/Os.
SDI, I/O
Serial Data Input
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO, TDO, I/O
Serial Data Output
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO is not available for 40MX devices.
TCK, I/O
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data
into the device. This pin functions as an I/O when the test
fuse is not programmed. BST pins are only available in
the A42MX24 and A42MX36 devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when the test fuse is not programmed. BST pins
are only available in the A42MX24 and A42MX36
devices.
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This
pin functions as an I/O when the test fuse is not
programmed. BST pins are only available in the
A42MX24 and A42MX36 devices.
TMS, I/O
Test Mode Select
Serial data input for boundary scan test mode. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when the test fuse is not programmed. BST pins
are only available in the A42MX24 and A42MX36
devices.
VCC
Supply Voltage Input
Input HIGH supply voltage for 40 MX devices.
VCCA
Supply Voltage Input
Input HIGH supply voltage, supplies array core for 42MX
devices.
VCCI
Supply Voltage Input
Input HIGH supply voltage, supplies I/O cells only for
42MX devices.
WD, I/O
Wide Decode Output
When a wide decode module is used in a 42MX device,
this pin can be used as a dedicated output from the wide
decode
module.
This
direct
connection
eliminates
additional interconnect delays associated with regular
logic modules. To implement the direct I/O connection,
connect an output buffer of any type to the output of
the wide decode macro and place this output on one of
the reserved WD pins. When a wide decode module is
not used, this pin functions as a regular I/O pin.
相關(guān)PDF資料
PDF描述
A40MX04-PLG68A FPGA, 6000 GATES, PQCC68
A42MX36-BG272A FPGA, 54000 GATES, PBGA272
A42MX36-BGG272A FPGA, 54000 GATES, PBGA272
A42MX36-CQ208A FPGA, 54000 GATES, CQFP208
A42MX36-CQ256A FPGA, 54000 GATES, CQFP256
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX04-PLG44I 功能描述:IC FPGA MX SGL CHIP 6K 44-PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-PLG44M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 44PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 34 I/O 44PLCC
A40MX04-PLG68 功能描述:IC FPGA 69I/O 68PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計(jì):226304 輸入/輸出數(shù):131 門(mén)數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28）
A40MX04-PLG68I 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-PLG68M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 68PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 57 I/O 68PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC
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