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| 型號(hào)： | A40MX04-VQG80A |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 6000 GATES, PQFP80 |
| 封裝： | PLASTIC, VQFP-80 |
| 文件頁(yè)數(shù)： | 28/78頁(yè) |
| 文件大?。?/td> | 515K |
| 代理商： | A40MX04-VQG80A |
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40MX and 42MX Automotive FPGA Families
1- 30
v3.0
Table 1-10 A40MX04 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C
Parameter
Description
Std. Speed
Units
Min.
Max.
Logic Module Propagation Delays1
tPD1
Single Module
2.2
ns
tPD2
Dual-Module Macros
4.7
ns
tCO
Sequential Clock-to-Q
2.2
ns
tGO
Latch G-to-Q
2.2
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.2
ns
Logic Module Predicted Routing Delays1
tRD1
FO=1 Routing Delay
2.4
ns
tRD2
FO=2 Routing Delay
3.4
ns
tRD3
FO=3 Routing Delay
4.3
ns
tRD4
FO=4 Routing Delay
5.2
ns
tRD8
FO=8 Routing Delay
9.0
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch) Data Input Set-Up
5.4
ns
tHD
3
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
5.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
5.8
ns
tWASYN
Flip-Flop (Latch)
5.8
ns
tA
Flip-Flop Clock Input Period
8.7
ns
fMAX
Flip-Flop (Latch) Clock Frequency
116
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.3
ns
tINYL
Pad-to-Y LOW
1.2
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
3.7
ns
tIRD2
FO=2 Routing Delay
4.6
ns
tIRD3
FO=3 Routing Delay
5.6
ns
tIRD4
FO=4 Routing Delay
6.5
ns
tIRD8
FO=8 Routing Delay
10.2
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
macro.
4. Delays based on 35 pF loading.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX04-VQG80I | 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-VQG80M | 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 80VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 80VQFP |
| A40MX09-PL84 | 制造商:Microsemi SOC Products Group 功能描述: |
| A40P24 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 White, fits 40x24, Steel |
| A-40P24 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 37.00x21.00 fits 40.00x2 |
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