參數(shù)資料
型號(hào)： A40MX04-VQG80A
元件分類： FPGA
英文描述： FPGA, 6000 GATES, PQFP80
封裝： PLASTIC, VQFP-80
文件頁(yè)數(shù)： 41/78頁(yè)
文件大?。?/td> 515K
代理商： A40MX04-VQG80A
40MX and 42MX Automotive FPGA Families
1- 42
v3.0
tRENSU
Read Enable Set-Up
1.0
ns
tRENH
Read Enable Hold
5.7
ns
tWENSU
Write Enable Set-Up
4.5
ns
tWENH
Write Enable Hold
0.0
ns
tBENS
Block Enable Set-Up
4.6
ns
tBENH
Block Enable Hold
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
13.6
ns
tRDADV
Read Address Valid
14.7
ns
tADSU
Address/Data Set-Up Time
2.7
ns
tADH
Address/Data Hold Time
0.0
ns
tRENSUA
Read Enable Set-Up to Address Valid
1.0
ns
tRENHA
Read Enable Hold
5.7
ns
tWENSU
Write Enable Set-Up
4.5
ns
tWENH
Write Enable Hold
0.0
ns
tDOH
Data Out Hold Time
2.0
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.7
ns
tINGO
Input Latch Gate-to-Output
2.4
ns
tINH
Input Latch Hold
0.0
ns
tINSU
Input Latch Set-Up
0.8
ns
tILA
Latch Active Pulse Width
7.8
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
3.3
ns
tIRD2
FO=2 Routing Delay
3.8
ns
tIRD3
FO=3 Routing Delay
4.4
ns
tIRD4
FO=4 Routing Delay
5.0
ns
tIRD8
FO=8 Routing Delay
7.2
ns
Table 1-14 A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C (Continued)
Parameter
Description
Std. Speed
Units
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A42MX36-1BG272B FPGA, 2438 CLBS, 36000 GATES, PBGA272
A42MX36-1BGG272B FPGA, 2438 CLBS, 36000 GATES, PBGA272
A42MX36-1PQ208B FPGA, 2438 CLBS, 36000 GATES, PQFP208
A42MX36-1PQ240B FPGA, 2438 CLBS, 36000 GATES, PQFP240
A42MX36-1PQG208B FPGA, 2438 CLBS, 36000 GATES, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX04-VQG80I 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-VQG80M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 80VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 80VQFP
A40MX09-PL84 制造商:Microsemi SOC Products Group 功能描述:
A40P24 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 White, fits 40x24, Steel
A-40P24 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 37.00x21.00 fits 40.00x2
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