參數(shù)資料
型號(hào)： A40MX04-VQG80A
元件分類(lèi)： FPGA
英文描述： FPGA, 6000 GATES, PQFP80
封裝： PLASTIC, VQFP-80
文件頁(yè)數(shù)： 42/78頁(yè)
文件大小： 515K
代理商： A40MX04-VQG80A
40MX and 42MX Automotive FPGA Families
v3.0
1-43
Global Clock Network
tCKH
Input Low to HIGH
FO = 32
4.5
ns
FO = 635
5.0
ns
tCKL
Input High to LOW
FO = 32
6.3
ns
FO = 635
8.1
ns
tPWH
Minimum Pulse Width HIGH
FO = 32
2.9
ns
FO = 635
3.3
ns
tPWL
Minimum Pulse Width LOW
FO = 32
2.9
ns
FO = 635
3.3
ns
tCKSW
Maximum Skew
FO = 32
1.1
ns
FO = 635
1.1
ns
tSUEXT
Input Latch External Setup
FO = 32
0.0
ns
FO = 635
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
4.8
ns
FO = 635
5.5
ns
tP
Minimum Period
FO = 32
8.6
ns
FO = 635
9.4
ns
fMAX
Maximum Frequency
FO = 32
116
MHz
FO = 635
107
MHz
TTL Output Module Timing1
tDLH
Data-to-Pad HIGH
4.3
ns
tDHL
Data-to-Pad LOW
5.0
ns
tENZH
Enable Pad Z to HIGH
4.4
ns
tENZL
Enable Pad Z to LOW
4.9
ns
tENHZ
Enable Pad HIGH to Z
8.8
ns
tENLZ
Enable Pad LOW to Z
8.3
ns
tGLH
G-to-Pad HIGH
5.0
ns
Table 1-14 A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C (Continued)
Parameter
Description
Std. Speed
Units
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A42MX36-1BG272B FPGA, 2438 CLBS, 36000 GATES, PBGA272
A42MX36-1BGG272B FPGA, 2438 CLBS, 36000 GATES, PBGA272
A42MX36-1PQ208B FPGA, 2438 CLBS, 36000 GATES, PQFP208
A42MX36-1PQ240B FPGA, 2438 CLBS, 36000 GATES, PQFP240
A42MX36-1PQG208B FPGA, 2438 CLBS, 36000 GATES, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX04-VQG80I 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-VQG80M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 80VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 80VQFP
A40MX09-PL84 制造商:Microsemi SOC Products Group 功能描述:
A40P24 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 White, fits 40x24, Steel
A-40P24 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 37.00x21.00 fits 40.00x2
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