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參數(shù)資料
| 型號： | A40MX04-VQG80A |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 6000 GATES, PQFP80 |
| 封裝： | PLASTIC, VQFP-80 |
| 文件頁數(shù)： | 4/78頁 |
| 文件大?。?/td> | 515K |
| 代理商： | A40MX04-VQG80A |
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40MX and 42MX Automotive FPGA Families
1- 8
v3.0
Design Consideration
It is recommended to use a series 70
termination
resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70
series termination is used
to prevent data transmission corruption during probing
and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test
(BST) Circuitry
Automotive-grade 42MX24 and 42MX36 devices are
compatible with IEEE Standard 1149.1 (informally known
as Joint Testing Action Group Standard or JTAG), which
defines a set of hardware architecture and mechanisms
for cost-effective, board-level testing. The basic MX
boundary-scan logic circuit is composed of the TAP (test
access port), TAP controller, test data registers and
instruction register (Figure 1-13). This circuit supports all
mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/
PRELOAD and BYPASS) and some optional instructions.
Table 1-3 on page 1-9 describes the ports that control
JTAG testing, while Table 1-4 on page 1-9 describes the
test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has
four associated pins: TCK (test clock input), TDI and TDO
(test data input and output), and TMS (test mode
selector).
The TAP controller is a four-bit state machine. The '1's
and '0's represent the values that must be present at TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles.
Automotive-grade 42MX24 and 42MX36 devices support
three types of test data registers: bypass, device
identification, and boundary scan. The bypass register is
selected when no other register needs to be accessed in a
device. This speeds up test data transfer to other devices
in a test data path. The 32-bit device identification
register is a shift register with four fields (lowest
significant byte (LSB), ID number, part number and
version). The boundary-scan register observes and
controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary-
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Figure 1-13 42MX IEEE 1149.1 Boundary Scan Circuitry
Boundary Scan Register
Instruction
Decode
Control Logic
TAP Controller
Instruction
Register
Bypass
Register
TMS
TCK
TDI
Output
MUX
TDO
JTAG
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX36-1BG272B | FPGA, 2438 CLBS, 36000 GATES, PBGA272 |
| A42MX36-1BGG272B | FPGA, 2438 CLBS, 36000 GATES, PBGA272 |
| A42MX36-1PQ208B | FPGA, 2438 CLBS, 36000 GATES, PQFP208 |
| A42MX36-1PQ240B | FPGA, 2438 CLBS, 36000 GATES, PQFP240 |
| A42MX36-1PQG208B | FPGA, 2438 CLBS, 36000 GATES, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX04-VQG80I | 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| A40MX04-VQG80M | 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 80VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 80VQFP |
| A40MX09-PL84 | 制造商:Microsemi SOC Products Group 功能描述: |
| A40P24 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 White, fits 40x24, Steel |
| A-40P24 | 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 37.00x21.00 fits 40.00x2 |
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