參數(shù)資料
型號(hào): A42MX16-1TQ100
廠商: Electronic Theatre Controls, Inc.
英文描述: XFRMR PWR 10.0VCT 8.0A QC .187
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 92/120頁
文件大?。?/td> 854K
代理商: A42MX16-1TQ100
73
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.3
Timer0 with Watchdog/Interval Timer
The Timer0 is a watchdog/interval timer which can be used to generate periodical interrupts and
as prescaler for Timer1, Timer2, Timer3 and the watchdog function.
Figure 3-27. Timer0 Block Diagram
The Watchdog/Interval Timer0 is clocked from a separate calibrated on-chip RC-Oscillator
(SRC) which runs at f
SCL = 90kHz. The SRC and the Timer0 can work together as an ultra low
power Watchdog/Interval timer stage.
The Timer0 consists of a programmable 20-stage divider that is driven by SCL. The timer output
signal (CLK
T0) can be used as prescaler clock and as source for the Timer0 interrupt. The inter-
rupt is able to mask via the T0IE bit and also the time interval for the timer output can be
adjusted as shown in Table 3-32 and Table 3-33 on page 78f via the T0PAS[2..0] and
T0PBS[2..0] bits in the Timer0 control register T0CR.
This timer starts running automatically after any power-on reset. If the watchdog function is not
activated, the timer can be restarted by writing a logic one to the T0PR bit in the T0CR register.
MUX-
Sensor Timer
WDPS2
WDPS1
WDPS0
T0PAS2
T0PAS1
T0PAS0
SCL
T0PR
T0PBS2
T0PBS1
T0PBS0
WD-RESET
INTT0
20-bit Timer 0 Watchdog Prescaler
MUX-
Sensor Timer
S
CL/512K
S
CL/
3
2K
S
CL/
3
2
S
CL/
3
2K
S
CL/1K
S
CL/
8
K
S
CL/
3
2K
S
CL/12
8
K
S
CL/4K
S
CL/256K
S
CL/1024K
MUX-
Watchdog Timer
SRCD
T0IE
Q3
WDE
Watchdog
Divider/8
Divider
Reset
Watchdog
Control
CLKWD
CLKSEN
CLKT0
Control
SRC-
Oscillator
S
CL/64K
S
CL/
8
K
S
CL/1K
S
CL/2K
S
CL/4K
S
CL/
3
2K
S
CL/256K
S
CL/512K
WDCE
WDR
S
CL/64K
S
CL/12
8
K
S
CL/256K
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