參數(shù)資料
型號: ACS8947T
廠商: Semtech
文件頁數(shù): 14/30頁
文件大小: 0K
描述: IC JITTER ATT MULT PLL 48-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 3G,以太網(wǎng),PCI,SONET/SDH,無線系統(tǒng)
輸入: LVPECL
輸出: CML,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 625MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN(7x7)
包裝: 托盤
ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 21
www.semtech.com
Where inputs to the ACS8947T are AC coupled, problems
may be experienced with activity detection. This is due to
noise/cross-talk on the inputs being interpreted as
activity. To avoid this, DC couple wherever possible and, if
AC coupling must be used, consider offsetting the DC bias
of the N and P signals. See Figure 15.
Figure 13 CML Output - DC Coupled to CML Receiver
Figure 14 JAM PLL CML Output DC coupled to LVPECL or
LVDS Receiver
Figure 15 Generic CML Output AC Coupled to LVPECL
Receiver
130/120R mismatch is used in the input bias network in
Figure 15 to emulate a simplified differential Schmitt
trigger, reducing the susceptibility to input noise when no
input is connected.
Figure 16 LVPECL Output - DC Coupled to LVPECL or LVDS
Receiver
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