參數(shù)資料
| 型號： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 4/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網，PCI，SONET/SDH，無線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 12
www.semtech.com
Lock Detector
A simple lock detector is incorporated. It combines the
plus and minus phase errors output from the PFD so that,
if any phase error signal is present, the LOCKB output
drives a PWM +10
μA current. The mark/space ratio
indicates the current input phase error.
By filtering this signal with a basic external RC parallel
filter as shown in Figure 6, a signal whose output level
indicates PLL phase and frequency lock is obtained.
Figure 6 Lock Detector External RC Filter
The filtering components are external so that the time to
indicate lock can be optimized for the application. The
output indicates both phase and frequency lock. During
off-frequency conditions, the LOCKB output is
predominately high.
Jitter Filtering
Input jitter is attenuated by the PLL with the frequency cut-
off point (Fc), at which jitter is tracked or attenuated,
defined by the -3 dB point: i.e. the position of the first pole
of the PLL loop filter. The bandwidth is the frequency at
which the first pole occurs and is defined by the
component value selected for the filter.
For a 19.44 MHz input, using a loop filter bandwidth of
2 kHz and damping factor of 1.2 gives:
High input jitter attenuation and roll off:
- 20 dB/decade from first loop filter pole, (Fc);
- 40 dB/decade from 2nd pole (typically 10 x Fc).
Jitter peaking is less than 1 dB (dependent on the
loop filter components);
Typical final output jitter: e.g. 2.8 ps RMS measured
over the integration range of 12 kHz to 20 MHz offset
from carrier.
Input Jitter Tolerance
Jitter tolerance is defined as the maximum amplitude of
sinusoidal jitter that can exist on the input reference clock
above which the device fails to acquire/maintain lock.
For the stand-alone device, the jitter tolerance for an
undivided reference (i.e. full rate PFD) is shown in
For frequencies below the PLL bandwidth, jitter tolerance
is seen to decrease at a rate of -20 dB per decade. For
jitter frequencies above the PLL bandwidth, jitter
tolerance is limited to 0.9 UI p-p.
Note...If the reference clock is divided, then the jitter tolerance
will be improved.
When the ACS8947T follows an ACS8525, the input jitter
tolerance is wholly defined by the latter. The system jitter
tolerance is dramatically increased due to the extended
phase capture range of the digital PLL within the
ACS8525.
Figure 7 Jitter Tolerance ACS8947T
Jitter Transfer
Jitter transfer is a ratio of input jitter present on the
reference clock to filtered jitter present on the output
clock. The ACS8947T jitter transfer characteristic is
defined solely by the loop filter bandwidth.
Figure 8 is an example showing the measured jitter
transfer characteristic on a 19.44 MHz reference clock
with a closed loop bandwidth of 2 KHz and a damping
factor of 1.2.
Input Jitter Tolerance With 2kHz PLL Bandwidth
0.01
0.1
1
10
100
1000
10
100
1000
10000
100000
1000000
Jitter Frequency Offset from Carrier (Hz)
In
p
u
t
Ji
tt
e
rA
m
p
lit
ud
e
p
-p
(
U
I)
ACS8946 Jitter
Tolerance
OC_12
Tolerance Mask
OC_48
Tolerance Mask
ACS8947
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