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參數(shù)資料
| 型號： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 2/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網(wǎng)，PCI，SONET/SDH，無線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 10
www.semtech.com
External feedback
An external feedback mode is available and can be used
for greater control of phase discrepancies: for example
when using external buffers. In external feedback mode,
the reference clock is presented to CLK1N/P and the
external feedback signal is presented to CLK2N/P. In this
mode, CLK1N/P is the only permitted input.
Source Switching
Figure 4 Simplified State Diagram of Source Switching
Figure 4 shows a simplified view of the automatic
switching behavior in the presence of activity alarms.
Signal ALARMC_CO3 from the PFD is used to disqualify a
clock, and signals ALARM1_CO0 and ALARM2_CO1
(representing no activity on input clocks CLK1 and CLK2
respectively), determine whether to select the remaining
clock. Switching between CLK1 and CLK2 is non-
revertive.
With ALARMC_CO3 providing a view of the currently
selected clock that is independent of the ALARM1_CO0
and ALARM2_CO1 signals, source selection behavior can
be more complex when these alarm signals disagree.
Consequently, to accommodate such behavior, the state
machine is necessarily more complex than that shown
here: e.g. when a clock signal is disconnected for a very
short period, or when an input clock is running at the
wrong frequency.
For more information, please contact Semtech Sales
Support.
Activity Alarms
Input activity monitors ALARM1_CO0 and ALARM2_CO1
flag the occurrence of six or more consecutive missing
cycles from inputs CLK1N/P and CLK2N/P. The alarm
signals operate on the input reference clock prior to the
internal PFD, and use an internal feedback clock from the
VCO to determine whether the reference clock has failed.
ALARMC_CO3 is an additional activity alarm that monitors
clock inputs to the PFD. This signal is more sensitive than
ALARM1_CO0 and ALARM2_CO1, triggering after three
missing clock edges to the PFD rather than at complete
failure of the input reference clock. Although alarm
ALARMC_CO3 has greater sensitivity than the input
activity monitor, it may take longer to assert if the input
divide ratio is greater than 2.
All activity monitor flags are low during normal operation
and active high when missing clock cycles are detected.
SYNC Input
In addition to the main input clock inputs, a single
differential SYNC input is provided. It provides a
resynchronization path to SYNC_OUT that is clocked and
synchronized to the rising edge of the OUT1 clock. The
SYNC input frequency should be limited to half the OUT1
clock rate, up to a maximum of 40 MHz. For correct
operation, the OUT1 output frequency should be at least
double that of the SYNC clock.
Input Divider DIVIP
The selected input clock is connected to the PFD via an
8-bit programable divider capable of division ratios from
1 to a maximum 256.
Feedback Divider DIVFB
The feedback path from the internal 2.35 GHz to 2.9 GHz
oscillator to the PFD includes a 9-bit programmable
divider that is capable of division ratios from 1 to a
maximum of 512. Depending on the chosen output
frequency, this divider is in series with a fixed divide-by-8
or the odd divider path described below.
Odd Divider DIVODD
The odd divider is capable of division ratios 1, 3, 5, 7,
9,11, 13 and 15. The output of the divider is connected to
the output multiplexing and divider stage. If odd number
division is used, the frequency adjustment factor applies
to all outputs - adjusting all selected output frequencies
proportionally.
Under some PLL configurations, the odd divider may also
be included in the feedback path to the PFD.
CLK 2
CLK 1
ALARMC_CO3 = 1
ALARM2_CO1 = 0
F8946D_012SimpStateDiag_01
ALARM SIGNALS:
ALARMC_CO3 -- Activity alarm for the currently selected clock (from PFD)
ALARM1_CO0 -- Activity alarm for CLK1
ALARM2_CO1 -- Activity alarm for CLK2
ALARMC_CO3 = 1
ALARM1_CO0 = 0
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