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參數(shù)資料
| 型號(hào)： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 6/30頁 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網(wǎng)，PCI，SONET/SDH，無線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 14
www.semtech.com
Figure 11 ACS8947T - Typical Closed Loop Transfer Function
Output Jitter
The output jitter meets all requirements of ITU, Telcordia
and ETSI standards for SONET rates up to 622.08 MHz
(OC-12/STM-4). See Electrical Specifications for details
on the jitter figures across the different output jitter
frequency bands relevant to each specification.
Device Reset
The RESETB pin is active low and requires a minimum
reset pulse duration of 100 ms once the power supplies
are stable and powered up. When the reset process is
triggered, the required PLL settings are decoded from the
configuration wiring connections, and the internal control
logic waits for the presence of an input signal of
approximately the correct frequency.
When a suitable input clock signal is detected, the
ACS8947T calibrates the VCO using a fast tuning
algorithm, and both frequency-lock and phase-lock to the
input reference. This calibration routine is run only after a
reset condition, so the RESETB pin should be held low
until the input frequency is within 200 ppm of nominal.
Layout Recommendations
It is highly recommended that a stable and filtered 3.3 V
power supply is used for the ACS8947T. A separate
filtered power and ground plane is recommended, with
supply decoupling capacitors of 10 nF and 100 pF
utilizing good, high-frequency chip capacitors (0402 or
0603 format surface mount package) on each VDD.
For optimum jitter cleaning performance, additional care
should be taken over the supply connection to VDDOSC,
which should be supplied directly from a 3.3 V LDO or a
4R7/68UF low-pass filter.
The wiring connections required for device configuration
are calcuated by the ACS8947T Evaluation Software GUI.
This program provides a schematic definition for the wired
connections to CFG[11:0] and includes a loop filter
component calculator.
Good differential signal layout on the input and output
lines should be used to ensure matched track impedance
and phase. Contact Semtech directly for further layout
recommendations.
Closed Loop
Gain GPO
Frequency
FPO
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