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參數(shù)資料
| 型號： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網(wǎng)，PCI，SONET/SDH，無線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 6
www.semtech.com
18
CFG_IN0
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
19
CFG_IN1
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
20
CFG_IN2
I
LVTTL/
LVCMOSD
Schmitt
Trigger
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
21
CFG_IN3
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
22
CFG_IN4
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
23
CFG_IN5
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
24
CFG_IN6
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
25
CFG_IN7
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
27
CLK1N
I
LVPECL
Negative differential input reference clock partnered with pin 28. Accepts a wide range of
input frequencies from 580 kHz to 180 MHz. Accepts LVPECL, LVDS or CML inputs given
suitable external interface components (see Input and Output Interface Terminations).
Selection between CLK1 and CLK2 is configurable between manual or automatic. See
28
CLK1P
I
LVPECL
Positive differential input reference clock partnered with pin 27. Accepts a wide range of
input frequencies from 580 kHz to 180 MHz. Accepts LVPECL, LVDS or CML inputs given
suitable external interface components (see Input and Output Interface Terminations).
Selection between CLK1 and CLK2 is configurable between manual or automatic. See
30
CLK2N
I
LVPECL
Negative differential input reference clock partnered with pin 31. Accepts a wide range of
input frequencies from 580 kHz to 180 MHz. Accepts LVPECL, LVDS or CML inputs given
suitable external interface components (see Input and Output Interface Terminations).
Selection between CLK1 and CLK2 is configurable between manual or automatic. See
31
CLK2P
I
LVPECL
Positive differential input reference clock partnered with pin 30. Accepts a wide range of
input frequencies from 580 kHz to 180 MHz. Accepts LVPECL, LVDS or CML inputs given
suitable external interface components (see Input and Output Interface Terminations).
Selection between CLK1 and CLK2 is configurable between manual or automatic. See
32
SEL_CLK2
I
LVTTL/
LVCMOSD
Used in combination with AUTO_SEL (pin 33) to select the CLK1 input (low) or CLK2 input
(high) in manual control mode, or to select automatic switching mode as described in
33
AUTO_SEL
I
LVTTL/
LVCMOSD
Used in combination with SEL_CLK2 (pin 32) to select automatic switching mode as
described in Table 5.
Table 3 Functional Pins (cont...)
Pin No.
Symbol
I/O
Type
Description
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| AD13280AZ | IC ADC 12BIT 68CLCC |
| AD1377KD | IC ADC SNGL 16BIT 32-CDIP |
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