VL DGND DRDY DRDYBUF = 0 DRDYBUF = 1 TO THE MICROPROCESSOR AD1556
參數(shù)資料
型號(hào)： AD1555BPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/24頁(yè)
文件大小： 0K
描述： IC ADC PGA 24BIT LN 28-PLCC
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 256k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 96mW
電壓電源： 雙 ±
工作溫度： -55°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 28-PLCC（11.51x11.51）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 1 個(gè)差分，雙極
其它名稱： AD1555BPZRLDKR
REV. B
AD1555/AD1556
–21–
AD1556
VL
DGND
DRDY
DRDYBUF = 0
DRDYBUF = 1
TO THE
MICROPROCESSOR
AD1556
VL
DRDY
TO THE
MICROPROCESSOR
TO OTHER
AD1556s
AD1556
VL
DRDY
DGND
Figure 11. DRDY Output Pin Configuration
Analog Input and Digital Output Data Format
When operating with a nominal MCLK frequency of 256 kHz,
the AD1555 is designed to output a ones-density bitstream from
0.166 to 0.834 on its MDATA output pin corresponding to an
input voltage from –2.25 V to +2.25 V on the MODIN pin.
The AD1556 computes a 24-bit two’s complement output whose
codes range from decimal –6,291,456 to +6,291,455 as shown
in Table VII.
Table VII. Output Coding
Analog Input
Output Code
MODIN
Hexa
Decimal
~ +2.526 V
*
5FFFFF
+6291455
~ +2.25 V
558105
+5603589
~ +2 V
4C00E8
+4980968
~ 0 V
000000
0
~ –2 V
B3FF17
–4980969
~ –2.25 V
AA7EFA
–5603590
~ –2.526 V
*
A00000
–6291456
*Input out of range.
STATUS Register
The AD1556 status register contains 24 bits that capture poten-
tial error conditions and readback the configuration settings.
The status register mapping is defined in Table VIII.
The
ERROR bit is the logical OR of the other error bits, OVWR,
MFLG, and ACC.
ERROR and the other error bits are reset
low after completing a status register read operation or upon
RESET. The
ERROR bit is the inverse of the ERROR output pin.
The OVWR bit indicates if an unread conversion result is over-
written in the output data register. If a data read was started but
not completed when new data is loaded into the output data
register, the OVWR bit is set high.
The MFLG status bit is set to the state of the MFLG input pin
on the rising edge of CLKIN. MFLG will remain set high as long
as the MFLG bit is set. The MFLG status bit will not change
during power-down or RESET.
The ACC bit is set high and the data output is clipped to either
+FS (0111 . . . ) or –FS (1000 . . . ) if an underflow or overflow
has occurred in the digital filter.
The FLSTL bit indicates the digital filter has settled and the
conversion results are an accurate representation of the analog
input. FLSTL is set low on RESET, at power-up, and upon
exiting the power-down state. FLSTL also goes low when SYNC
sets the start of the filter’s convolution cycle, when changes are
made to the device setting with the hardware pins CB0–CB4,
BW0–BW2, or CSEL, and when the MFLG status bit is set
high. When FLSTL is low the OVWR, MFLG, ACC, and DRNG
status bits will not change.
The DRNG bit is used to indicate if the analog input to the
AD1555 is outside its specified operating range. The DRNG bit
is set high whenever the AD1556 digital filter computes four
consecutive output samples that are greater than decimal
+6,291455 or all less than –6,291456.
Layout
The AD1555 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
The printed circuit board that houses the AD1555 and the
AD1556 should be designed so the analog and digital sections
are separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
Digital and analog ground planes should be joined in only one
place, preferably underneath the AD1555, or at least as close as
possible to the AD1555. If the AD1555 is in a system where
multiple devices require analog-to-digital ground connections,
the connection should still be made at one point only, a star
ground point, which should be established as close as possible to
the AD1555.
It is recommended to avoid running digital lines under the
device since these will couple noise onto the die. The analog
ground plane should be allowed to run under the AD1555 to
avoid noise coupling. Fast switching signals such as MDATA and
MCLK should be shielded with digital ground to avoid radiating
noise to other sections of the board and should never run near
analog signal paths. Crossover of digital and analog signals
should be avoided. Traces on different but close layers of the
board should run at right angles to each other. This will re-
duce the effect of feedthrough through the board.
The power supply lines to the AD1555 should use as large a
trace as possible to provide low impedance paths and reduce
the effect of glitches on the power supply lines. Good decoupling
is also important to lower the supplies impedance resent to the
AD1555 and reduce the magnitude of the supply spikes. Decou-
pling ceramic capacitors, typically 100 nF, should be placed on
power supply pins +VA, –VA, and VL close to, and ideally right
up against these pins and their corresponding ground pins.
Additionally, low ESR 10
F capacitors should be located in
the vicinity of the ADC to further reduce low frequency ripple.
The VL supply of the AD1555 can either be a separate supply
or come from the analog supply VA. When the system digital
supply is noisy, or fast switching digital signals are present, it is
recommended, if no separate supply is available, to connect the
VL digital supply to the analog supply VA through an RC filter
as shown in Figure 7.
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