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參數(shù)資料
| 型號： | AD1555BPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC PGA 24BIT LN 28-PLCC |
| 標準包裝： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 256k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 96mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -55°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 其它名稱： | AD1555BPZRLDKR |
REV. B
AD1555/AD1556
–18–
When the VREF input is selected, S4(+) and S4(–) are closed, all
the other switches are opened, and a reference voltage (2.25 V)
equal to half of the full-scale range is sampled. In this combina-
tion, the gain setting is forced to be the gain of 1.
When the signal input is selected, S1(+) and S1(–) are closed, all
the other switches are opened, and the differential input signal
between AIN(+) and AIN(–) is sampled. This is the main path
for signal acquisition.
When the test input is selected, S2(+) and S2(–) are closed, all
the other switches are opened, and the differential input signal
between TIN(+) and TIN(–) is sampled. This combination
allows acquisition of a test signal or a secondary channel with
the same level of performance as with AIN inputs. By applying
known voltages to these inputs, it is also possible to calibrate the
gain for each gain setting.
When the Sensor Test 1 is selected, S1(+), S1(–), S2(+), and
S2(–) are closed, all the other switches are opened, and the gain
setting is forced to be the gain of 1. In this configuration, a
source between TIN(+) and TIN(–) may be applied to the
sensor to determine its impedance or other characteristics. The
total internal serial resistance between each AIN input and the
PGA inputs, nominally 66
, slightly affects these measurements.
The total internal serial resistance between each TIN input and
the PGA inputs is nominally 116
.
When the Sensor Test 2 is selected, S1(+), S2(+), and S2(–)
are closed, all the other switches are opened. This configuration
could be used to test the sensor isolation.
Power-Down Modes of the AD1555
The AD1555 has two power-down modes. The multiplexer and
programmable gain amplifier can be powered down by the
CB2–CB0 setting of “101.” The entire chip is powered down by
either CB2–CB1 set to “11” or by keeping the clock input MCLK
at a fixed level high or low. Less shutdown current flows with
MCLK low. The least power dissipation is achieved when the
external reference is shut down eliminating the current through
the 30 k
nominal load at REFIN. When in power-down, the
multiplexer is switched to the “ground input.”
DAC
MDATA
LOOP FILTER
FS
RIN
20k
COMPARATOR
INTEGRATOR
MODIN
Figure 9. Sigma-Delta Modulator Block Diagram
SIGMA-DELTA MODULATOR
The AD1555 sigma-delta modulator achieves its high level of
performance, notably in dynamic range and distortion, through
the use of a switched-capacitor feedback DAC in an otherwise
continuous-time design. Novel circuitry eliminates the subtle
distortion normally encountered when these disparate types are
connected together. As a result, the AD1555 enjoys many of the
benefits of both design techniques.
Because of the switched-capacitor feedback, this modulator is
much less sensitive to timing jitter than is the usual continuous-
time design that relies on the duty cycle of the clock to control a
switched-current feedback DAC.
Unlike its fully switched-capacitor counterparts, the modulator
input circuitry is nonsampling, consisting simply of an internal,
low temperature coefficient resistor connected to the summing
node of the input integrator. Among the advantages of this
continuous-time architecture is a relaxation of requirements for
the antialias filter; in fact, the output of the programmable gain
amplifier, PGAOUT, may be tied directly to the input of the
modulator MODIN without any external filter. Another advan-
tage is that the gain may be adjusted to accommodate a higher
input range by adding an external series resistor at MODIN.
The modulator of the AD1555 is fourth order, which very effi-
ciently shapes the quantization noise so that it is pushed toward
the higher frequencies (above 1 kHz) as shown in TPC 3. This
high frequency noise is attenuated by the AD1556 digital filter.
However, when the output word rate (OWR) of the AD1556 is
higher than 4 kHz (–3 dB frequency is higher than 1634 Hz),
the efficiency of this filtering is limited and slightly reduces the
dynamic range, as shown in the Table I. Hence, when possible,
an OWR of 2 kHz or lower is generally preferred.
Sigma-delta modulators have the potential to generate idle tones
that occur for dc inputs close to ground. To prevent this unde-
sirable effect, the AD1555 modulator offset is set to about –60 mV.
In this manner, any existing idle tones are moved out of the
band of interest and filtered out by the digital filter.
Also, sigma-delta modulators may oscillate when the analog
input is overranged. To avoid any instability, the modulator of
the AD1555 includes circuitry to detect a string of 16 identical
bits (“0” or “1”). Upon this event, the modulator is reset by
discharging the integrator and loop filter capacitors and MFLG
is forced high. After 1.5 MCLK cycles, MFLG returns low.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1556 | 制造商:AD 制造商全稱:Analog Devices 功能描述:24-Bit ADC WITH LOW NOISE PGA |
| AD1556AS | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 256ksps 24-bit Parallel/Serial 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1556ASRL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 256ksps 24-bit Parallel/Serial 44-Pin MQFP T/R |
| AD1556ASZ | 功能描述:IC ADC PGA 24BIT LN 44MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD1556ASZRL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 256ksps 24-bit Parallel/Serial 44-Pin MQFP T/R |
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