- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373859 > AD1801 (Analog Devices, Inc.) Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器) PDF資料下載
參數(shù)資料
| 型號(hào)： | AD1801 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器) |
| 中文描述： | 單芯片傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語音調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AD1801 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD1801
–26–
REV. 0
cycle can take from 2.5 to a maximum of 3.5 DSP cycles to
complete. One or two cycles are required for synchronization,
then there is a half cycle setup time for the
IACK
control, fol-
lowed by the single data transfer cycle.
If data cannot be presented onto the PC Card Bus within 100 ns
from the falling edge of a read strobe using either the long or
short IDMA Read Cycle timing, a data prefetch mechanism for
every address counter update will be required. Internal holding
registers can be used, essentially, to create a 1-word deep FIFO
or to create a word register pair employing a ping-pong access
arrangement, in order to meet PC Card Bus timing requirements.
Synchronous Serial Port
The AD1801 provides an external synchronous serial port
(identical to the SPORT module in the ADSP-2181) that can
be optionally selected in place of the second external function
under the PCMCIA module’s control. The Port Mode (PM) bit
in the DSP Control register is used to select the enable option.
Power-Down Modes
The power-down control pins,
PWD
and PWDACK, available
on the ADSP-2181, are brought out of the AD1801 to provide
a hardware option for putting the DSP core in a low power
state. The active HI PWDACK control indicates when the
processor is powered down; it is deactivated when the processor
has completed its power-up sequence. A logic LO on this pin
also indicates that the processor’s CLKOUT signal is valid and
that program execution has begun.
General Purpose I/O Port
The AD1801 provides eight bits of general I/O, IO(7:0), that
can be programmed by the DSP. The I/O Port Control (IPC)
register determines port bit direction; a logic “0” sets a port bit
to an output while a logic “1” sets a port bit to an input. Each
port bit is tied to an internal weak pull-up resistor.
The AD1801 provides a single 8-bit output port register that is
programmed by the DSP. Input port bits are not registered;
they are simply passed onto the DSP data bus (D[15:0]) during
active read operations accessing the DSP Input Port. Note that
the DSP will read the internally generated output port bits that are
active along with the active externally supplied input port bits.
The eight programmable I/O pins on the AD1801 (Pins 33
through 40) will source between 170
μ
A and 340
μ
A when they
are three-stated. This feature provides weak pull-up capability
from power-on. This current sourcing capacity should only be
used to determine how fast the AD1801 will pull up the pin and
how much current devices driving the AD1801’s I/O pins need to
sink to drive to logic LO.
When configured as outputs, the I/O pins will source 0.5 mA at
2.4 V (HI level output voltage) and will sink 2.0 mA at 0.4 V (LO
level output voltage). They are conservative ratings for 10 ns edge
transitions with a 50 pF load.
JTAG Scanning Logic
JTAG boundary scan logic is included in the AD1801.
The AD1801 is compliant with IEEE std. 1149.1a-1993. Only
the mandatory instructions are supported. These are: BYPASS,
SAMPLE/PRELOAD, and EXTEST. Scan order, from first in
to last in, as follows.
Table VI. JTAG Scan Order
0 PCM_
ISA
1 PNP_
STD
2 RESET
3
RESET
4
ERESET
5 TESTB (DV
DD
) 48 TFS/
RS
2
6 ELIN
7
EINT
8 ECLK
9
EBR
10 EE
11
EBG
12
EMS
OutEn
13
EMS
14 ELOUT
15 IO7 OutEn
16 IO7
17 IO6 OutEn
18 IO6
19 IO5 OutEn
20 IO5
21 IO4 OutEn
22 IO4
23 IO3 OutEn
24 IO3
25 IO2 OutEn
26 IO2
27 IO1 OutEn
28 IO1
29 IO0 OutEn
30 IO0
31 SEN OutEn
32 SEN
33 SDATA OutEn
34 SDATA
35 SCK OutEn
36 SCK
37 RING
38 XTALI
39 XTALO
40
PDW
41 PWDACK
42 DR/INT2
43 RFS/CS2 OutEn
44 RFS/
CS
2
45 DT/PD2 OutEn
46 DR/PD2
47 TFS/
RS
2 OutEn
86 IRQ15/VCTL2
87 IRQ12/PD1 OutEn
88 IRQ12/PD1
89 IRQ11/
RS
1 OutEn
90 IRQ11/
RS
1
91 IRQ10/
CS
1 OutEn
92 IRQ10/
CS
1
93 IRQ9/
IREQ
OutEn
94 IRQ9/
IREQ
95 IRQ7/
SPKR
OutEn
96 IRQ7/
SPKR
97 IRQ5/
CHG
OutEn
98 IRQ5/
CHG
99 IRQ4/
INPK
OutEn
100 IRQ4/
INPK
101 IRQ3/VCTL1 OutEn
102 IRQ3/VCTL
103 IOCHRDY/
WAIT
OutEn
104 IOCHRDY/
WAIT
105
IOW
106
IOR
107 AEN/
REG
108
SBHE
/
CE2
109 SA15/
CE1
110 SA14/INT1
111 SA13/
WE
112 SA12/
OE
113 SA11
114 SA10
115 SA9
116 SA8
117 SA7
118 SA6
119 SA5
120 SA4
121 SA3
122 SA2
123 SA1
124 SA0
49 SCLK OutEn
50 SCLK
51 SD15 OutEn
52 SD15
53 SD14 OutEn
54 SD14
55 SD13 OutEn
56 SD13
57 SD12 OutEn
58 SD12
59 SD11 OutEn
60 SD11
61 SD10 OutEn
62 SD10
63 SD9 OutEn
64 SD9
65 SD8 OutEn
66 SD8
67 SD7 OutEn
68 SD7
69 SD6 OutEn
70 SD6
71 SD5 OutEn
72 SD5
73 SD4 OutEn
74 SD4
75 SD3 OutEn
76 SD3
77 SD2 OutEn
78 SD2
79 SD1 OutEn
80 SD1
81 SD0 OutEn
82 SD0
83
IOCS16
/
IOIS16
OutEn
84
IOCS16
/
IOIS16
85 IRQ15/VCTL2 OutEn
NOTE
The JTAG input
TRS
(Pin 122) must be connected to digital ground (which
dissipates a small amount of power due to the on-chip weak pull-up device) or to
RESET
(recommended) to ensure reliable AD1801 operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1803JRU | U.S./International Modem DAA Line Codec Chipset |
| AD1803 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1804 | U.S./International Modem DAA Line Codec Chipset |
| AD1804JRU | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD1812JST | Silver Mica Capacitor; Capacitance:12pF; Capacitance Tolerance: 5%; Series:CD17; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:5.9mm; Leaded Process Compatible:No RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1801JS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1801JST-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1803 | 制造商:AD 制造商全稱:Analog Devices 功能描述:U.S./International Modem DAA Line Codec Chipset |
| AD1803-0.4 | 制造商:Analog Devices 功能描述: |
| AD1803JRU | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。