參數(shù)資料
型號(hào)： AD1801
廠商： Analog Devices, Inc.
英文描述： Single-Chip Fax/Data/ Voice Modem(單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器)
中文描述： 單芯片傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器（單片的傳真/數(shù)據(jù)/語(yǔ)音調(diào)制解調(diào)器）
文件頁(yè)數(shù)： 43/52頁(yè)
文件大?。?/td> 348K
代理商： AD1801
AD1801
–43–
REV. 0
POWER CONSUMPTION
The AD1801 power consumption is dependent on many factors,
including codec resources used, ADSP-2181 core resources used
and instruction mix. Table XII provides some estimates of the
maximum current consumption of the AD1801 as a function of
device resources used.
Table XII. AD1801 Current Consumption Estimates
Power
States
System Bus
Interface
Estimated
Max Current
DSP
Codec
1MHS* Active
Up: Mod & Hnd
& Spk Enabled
Up: Mod & Hnd
Enabled
Up: Spk Enabled
Up: Hnd Enabled Responsive
Up: Mod Enabled Responsive
Up: All Channels
Disabled
Standby
Down
Down
Standby
Down
Standby Standby
Responsive
252 mA
1MH*
Active
Responsive
157 mA
1S*
1H*
1M*
1
Active
Active
Active
Active
Responsive
220 mA
142 mA
140 mA
125 mA
Responsive
2C
2
R
3C
3
4C
Active
Active
NOP
Idle
Idle
Responsive
Responsive
Nonresponsive
Responsive
Responsive
Slow
Responsive
Slow
Responsive
Nonresponsive
Nonresponsive
94 mA
92 mA
40 mA
19 mA
17 mA
≈
5 mA
4
Standby Down
≈
3 mA
5C
5
Down
Down
Standby
Down
2.5 mA
0.5 mA
*When in Power State 1, any combination of the Modem (Mod), Handset (Hnd),
and Speaker (Spk) channels may be enabled through the use of independent
channel enable bits (see the DSP I/O mapped CC register). Only the combina-
tions thought most likely to be used have been listed.
*
Current numbers assume:
1. 50% of instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are
1.
Type 2 and Type 6, and 20% are idle.
2. Device is operating with no ISA/PCMCIA pin loads.
WARNING: For proper operation of the AD1801, DSP code
must never:
1. Use the IDLE(n) instruction (critical internal clocks will be
slowed).
2. Write the PDFORCE (power-down interrupt force) bit in
the SPORT1 Autobuffer Control Register to “1” (this would
power down the AD1801 with no means of powering back up
other than a pin reset).
Power-Down States
Power State R
DSP:
Codec:
Interface:
Crystal:
The AD1801 is forced into this Power State any time one or
both of the reset pins (RESET and
RESET
) is asserted. The
AD1801 will remain in this Power State until both of the reset
pins are deasserted. Immediately after both reset pins are
deasserted, the AD1801 will enter Power State 2 and commence
instruction execution at location 0x2000 ROM.
When power is first applied, the AD1801 must be kept in this
Power State (by the continuous assertion of at least one of the
Running NOP
Powered Down
Nonresponsive
Enabled
reset pins) until the clock input on the XTALI pin stabilizes,
plus another 1000 XTALI cycles to allow the AD1801’s phase
locked loop to lock. With a crystal connected between the
XTALI and XTALO pins, the time required for the clock input
to stabilize is dependent upon the type of crystal used and the
capacitance of the external crystal circuit; typically 2000 XTALI
cycles is adequate.
If the AD1801 was in Power State 5 prior to the assertion of
a pin reset, the procedure listed above for initial power-up
must be followed since the clocks were stopped while in Power
State 5.
If the AD1801 was in Power State 1, 2, 3 or 4 prior to the asser-
tion of a reset pin, the AD1801 must be kept in this Power State
(by the continuous assertion of at least one of the reset pins) for
at least five XTALI cycles. Note that asserting a reset while in
Power State 1 is not recommended due to the “noisy” abrupt
shutdown of the codec.
Power State 2
DSP:
Active
Codec:
Powered Down or in Standby
Interface:
Responsive
Crystal:
Enabled
If the codec is in standby (see the SBEN bit in DSP I/O mapped
register CC), its voltage reference circuitry is not powered down
which results in greater power consumption; however, the time
required to transition from Power State 2 to Power State 1 is
decreased from approximately 500 ms to approximately 15 ms.
If the CEN (Codec Enable) bit is set to “1” (see DSP I/O
mapped register CC), the process of entering Power State 1 will
be initiated. The DSP may poll the codec (by reading the CEN
bit and waiting for an echo of “1”) to determine when Power
State 1 is actually entered.
Power State 3 will be entered if an IDLE instruction is executed
by the DSP, provided the DSP is not currently servicing a
power-down interrupt. Note that the IDLE(n) DSP instruction
must not be used since the internal clock slow down caused by
this instruction will interfere with the AD1801 bus interface
logic.
Power State 1 (Any Form)
DSP:
Active
Codec:
Powered up. Any combination of Modem,
Handset and Speaker Codec Channels
Enabled.
Interface:
Responsive
Crystal:
Enabled
Although the codec is powered up in this Power State, the
amount of power actually consumed is still dependent on the
number of codec channels actually enabled. The modem (ADC
and DAC), handset (ADC and DAC) and speaker (DAC) chan-
nels can be independently enabled and disabled using the MEN,
HEN and MSEN bits in DSP I/O mapped register CC.
Before enabling either the modem of handset codec channels,
the DSP serial port used to communicate with the codec chan-
nels must first be properly configured in the DSP. If serial port
0 is used, the “SPORT 0 Control” register at 0x3FF6 must be
set to 0x3C0F. If serial port 1 is used, the “SPORT 1 Control”
register at 0x3FF2 must be set to 0x3C0F. Also, the used serial
ports must be enabled by setting the appropriate bits in the
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