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參數(shù)資料
| 型號： | AD1852JRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO 24BIT 28-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，I²S，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 265mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | 192k |
AD1852
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND 1
MCLK 2
CLATCH 3
CCLK 4
DVDD
28
SDATA
27
BCLK
26
LRCLK
25
CDATA 5
NC 6
192/48 7
RESET
24
MUTE
23
ZEROL
22
ZEROR 8
IDPM0
21
DEEMP 9
IDPM1
20
96/48 10
FILTB
19
AGND 11
AVDD
18
OUTR+ 12
OUTL+
17
OUTR– 13
OUTL–
16
FILTER 14
AGND
15
TOP VIEW
(Not to Scale)
AD1852
08
45
7-
00
2
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
Mnemonic
Input/Output
Description
1
DGND
I
Digital Ground.
2
MCLK
I
Master Clock Input. Connect to an external clock source running at either 256 fS, 384 fS, 512 fS,
768 fS, or 1024 fS.
3
CLATCH
I
Latch Input for SPI Control Data Port. This input is rising-edge sensitive.
4
CCLK
I
SPI Control Clock Input for Control Data. Control input data must be valid on the rising edge of
CCLK. CCLK may be continuous or gated.
5
CDATA
I
SPI Control Data Input, MSB First. SPI data port for controlling AD1852 functions as described in
the SPI Register Definitions section.
6
NC
No Connect.
7
192/48
I
192 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 192 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 11 of the control register.
8
ZEROR
O
Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input
for more than 1024 LR clock cycles.
9
DEEMP
I
De-Emphasis. Digital de-emphasis is enabled when this input signal is high. This is used to
impose a 50 μs/15 μs response characteristic on the output audio spectrum at an assumed
44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via the SPI
control register.
10
96/48
I
96 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 96 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 10 of the control register.
11, 15
AGND
I
Analog Ground.
12
OUTR+
O
Right Channel Positive Line Level Analog Output.
13
OUTR
O
Right Channel Negative Line Level Analog Output.
14
FILTR
O
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference
with parallel 10 μF and 0.1 μF capacitors to the AGND.
16
OUTL
Left Channel Negative Line Level Analog Output.
17
OUTL+
O
Left Channel Positive Line Level Analog Output.
18
AVDD
I
Analog Power Supply. Connect this pin to the analog 5 V supply.
19
FILTB
Filter Capacitor Connection. Connect 10 μF||10 nF capacitor to AGND (Pin 15).
20
IDPM1
I
Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
21
IDPM0
I
Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
22
ZEROL
O
Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input
for more than 1024 LR clock cycles.
23
MUTE
I
Mute. Assert this pin high to mute both stereo analog outputs. De-assert low for normal operation.
24
RESET
I
Reset. The AD1852 is reset on the rising edge of this signal. The serial control port registers are
reset to the default values. For normal operation, assert this pin high.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1853 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Stereo, 24-Bit, 192 kHz, Multibit DAC |
| AD1853JRS | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:STEREO, 192KHZ MULTIBIT SIGMA DELTA DAC - Bulk 制造商:Analog Devices 功能描述:IC STEREO 24-BIT DAC |
| AD1853JRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:STEREO, 192KHZ MULTIBIT SIGMA DELTA DAC - Bulk |
| AD1853JRSZ | 功能描述:IC DAC STEREO 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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