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參數(shù)資料
| 型號： | AD1852JRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO 24BIT 28-SSOP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,500 |
| 位數(shù)： | 24 |
| 數(shù)據接口： | DSP，I²S，串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 265mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | 192k |
AD1852
Rev. A | Page 13 of 20
BCLK
LRCLK
SDATA
LEFT-JUSTIFIED
MODE
SDATA
I2C-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
LSB
tDBH
tDBP
tDBL
tDLS
tDDS
tDDH
tDDS
tDDH
tDDS
tDDH
tDDS
tDDH
MSB
MSB – 1
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
08
45
7-
02
6
Figure 26. Serial Data Port Timing
Table 13. Allowable MCLK Frequencies and Internal Delta Clock Rates
Chip Mode
Allowable Master Clock Frequencies
Nominal Input Sample Rate (kHz)
Internal Sigma-Delta Clock Rate
INT 8× Mode
256 × fS, 384 × fS, 512 × fS, 768 × fS, 1024 × fS
48
128 × fS
INT 4× Mode
128 × fS, 192 × fS, 256 × fS, 384 × fS, 512 × fS
96
64 × fS
INT 2× Mode
64 × fS, 96 × fS, 128 × fS, 192 × fS, 256 × fS
192
32 × fS
D15
D14
D0
tCHD
tCLH
tCLL
tCLSU
tCCL
tCCH
tCSU
CDATA
CCLK
CLATCH
0
84
57
-02
7
Figure 27. Serial Control Port Timing
MASTER CLOCK AUTODIVIDE FEATURE
The AD1852 has a circuit that autodetects the relationship between
the master clock and the incoming serial data and internally sets
the correct divide ratio to run the interpolator and modulator. The
allowable frequencies for each mode are shown in Table 13.
Master clock should be synchronized with LRCLK; however,
phase relation between master clock and LRCLK is not critical.
SPI REGISTER DEFINITIONS
The SPI port allows flexible control of many chip parameters. It
is organized around three registers: a left-channel volume register, a
right-channel volume register, and a control register. Each write
operation to the AD1852 SPI control port requires 16 bits of
serial data in MSB-first format. The bottom two bits are used to
select one of three registers, and the top 14 bits are then written
to that register. This allows a write to one of the three registers
in a single 16-bit transaction.
The SPI CCLK signal is used to clock in the data. The incoming
data should change on the falling edge of this signal. At the end
of the 16 CCLK periods, the CLATCH signal should rise to
clock the data internally into the AD1852.
The serial control port timing is shown in Figure 27, and the
SPI digital timing values are listed in Table 14.
Table 14. SPI Digital Timing
Parameter
Description
Value
tCCH
CCLK high pulse width
40 ns
tCCL
CCLK low pulse width
40 ns
tCSU
CDATA setup time
10 ns
tCHD
CDATA hold time
10 ns
tCLL
CLATCH low pulse width
10 ns
tCLH
CLATCH high pulse width
10 ns
tCLSU
CLATCH setup time
4 × tMCLK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD1853 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Stereo, 24-Bit, 192 kHz, Multibit DAC |
| AD1853JRS | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:STEREO, 192KHZ MULTIBIT SIGMA DELTA DAC - Bulk 制造商:Analog Devices 功能描述:IC STEREO 24-BIT DAC |
| AD1853JRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:STEREO, 192KHZ MULTIBIT SIGMA DELTA DAC - Bulk |
| AD1853JRSZ | 功能描述:IC DAC STEREO 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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