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參數(shù)資料
| 型號(hào)： | AD1852JRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO 24BIT 28-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，I²S，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 265mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | 192k |
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AD1852
Rev. A | Page 12 of 20
THEORY OF OPERATION
SERIAL DATA INPUT PORT
The flexible, serial data input port of the AD1852 accepts data
in twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by either using the external mode pins (IDPM0, Pin 21 and
IDPM1, Pin 20) or the mode select bits (Bit 4 and Bit 5) in the
SPI control register. To control the serial mode using the
external mode pins, the SPI mode select bits should be set to
zero (the default mode at power-up). To control the serial mode
using the SPI mode select bits, the external mode control pins
should be grounded.
In all modes, except for right-justified mode, the serial port
accepts an arbitrary number of bits up to 24. Extra bits do not
cause an error, but they are truncated internally. In right-
justified mode, use Bit 8 and Bit 9 of the SPI control register to
set the word length to 16 bits, 20 bits, or 24 bits. The default
mode at power-up is 24-bit mode. When the SPI control port is
not being used, the SPI pins (CLATCH, CCLK, and CDATA
[Pin 3, Pin 4, and Pin 5]) should be tied low.
SERIAL DATA INPUT MODE
The AD1852 uses two multiplexed input pins to control the
mode configuration of the input data port mode (see Table 12).
Figure 3 shows the right-justified mode (16 bits shown). LRCLK is
high for the left channel and low for the right channel. Data is
valid on the rising edge of BCLK.
In normal operation, there are 64-bit clocks per frame (or 32 per
half frame). When the SPI word length control bits (Bit 8 and
Bit 9 in the SPI control register) are set to 24 bits (0:0), the serial
port begins to accept data starting at the eighth bit clock pulse
after the LRCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 16-bit mode, data is accepted starting at the
16th bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore, other data formats
are possible using the delay values previously described. For
detailed timing, see Figure 26.
and high for the right channel. Data is valid on the rising edge
of BCLK. The MSB is left justified to an LRCLK transition but
with a single BCLK period delay. The I2S mode can be used to
accept any number of bits up to 24.
Figure 5 shows the left-justified mode. LRCLK is high for the
left channel, and low for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an LRCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits, and any number of bit
clocks from two times the word length to 64-bit clocks per
frame.
Figure 6 shows the DSP serial port mode. LRCLK must pulse
high for at least one bit clock period before the MSB of the left
channel is valid, and LRCLK must pulse high again for at least
one bit clock period before the MSB of the right channel is
valid. Data is valid on the falling edge of BCLK. The DSP serial
port mode can be used with any word length up to 24 bits.
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse and that
synchronism is maintained from that point forward.
Note that the AD1852 is capable of a 32 × fS BCLK frequency
packed mode, where the MSB is left justified to an LRCLK
transition, and the LSB is right justified to the opposite LRCLK
transition. LRCLK is high for the left channel and low for the
right channel. Data is valid on the rising edge of BLCK. Packed
mode can be used when the AD1852 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 7.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1853 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Stereo, 24-Bit, 192 kHz, Multibit DAC |
| AD1853JRS | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:STEREO, 192KHZ MULTIBIT SIGMA DELTA DAC - Bulk 制造商:Analog Devices 功能描述:IC STEREO 24-BIT DAC |
| AD1853JRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:STEREO, 192KHZ MULTIBIT SIGMA DELTA DAC - Bulk |
| AD1853JRSZ | 功能描述:IC DAC STEREO 24BIT 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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