I 2S Mode In I 2S Mode, the da" />
參數(shù)資料
型號： AD1871YRSZ
廠商： Analog Devices Inc
文件頁數(shù)： 10/28頁
文件大?。?/td> 0K
描述： IC ADC STEREO AUDIO 24BIT 28SSOP
產(chǎn)品培訓(xùn)模塊： Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝： 47
位數(shù)： 24
采樣率（每秒）： 96k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸入數(shù)目和類型： 4 個單端，單極
產(chǎn)品目錄頁面： 777 (CN2011-ZH PDF)
AD1871
–18–
REV. 0
I
2S Mode
In I
2S Mode, the data is left-justified, MSB first, with the MSB
placed in the second BCLK period following the transition of
the LRCLK. A high-to-low transition of the LRCLK signifies
the beginning of the left channel data transfer, while a low-to-
high transition on the LRCLK signifies the beginning of the
right channel data transfer (see Figure 12).
LEFT CHANNEL
RIGHT CHANNEL
MSB–2
MSB–1
LSB+2
LSB+1
LSB
MSB–2
MSB–1
MSB
LSB+2 LSB+1
LSB
MSB
LRCLK
BCLK
DOUT
MSB
Figure 12. I2S Mode
LJ Mode
In LJ Mode, the data is left-justified, MSB first, with the MSB
placed in the first BCLK period following the transition of the
LRCLK. A high-to-low transition of the LRCLK signifies the
beginning of the right channel data transfer, while a low-to-high
transition on the LRCLK signifies the beginning of the left
channel data transfer (see Figure 13).
MSB–2
MSB–1
LSB+2
LSB+1
LSB
MSB–2
MSB–1
MSB
LSB+2
LSB+1
LSB
MSB–1
MSB
LRCLK
BCLK
DOUT
LEFT CHANNEL
RIGHT CHANNEL
MSB
Figure 13. Left-Justified Mode
RJ Mode
In RJ Mode, the data is right-justified, LSB last, with the
LSB placed in the last BCLK period preceding the transition
of the LRCLK. A high-to-low transition of the LRCLK signifies
the beginning of the right channel data transfer, while a low-to-
high transition on the LRCLK signifies the beginning of the left
channel data transfer (see Figure 14).
DOUT
LSB
MSB–2
MSB–1
LSB+2 LSB+1
MSB–2
MSB–1
MSB
LSB+2 LSB+1
LSB
BCLK
LRCLK
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Figure 14. Right-Justified Mode
DSP Mode
In DSP Mode, the LRCLK signal becomes a frame sync signal
that pulses high for the BCLK period prior to the MSB (or in
the BCLK period of the previous LSB–32 bits). The data is left-
justified, MSB first, with the MSB placed in the BCLK period
following the LRCLK pulse (see Figure 15).
In I
2S and LJ Modes, since the data is left-justified, differences in
data word-width between the AD1871 and the controller are not
catastrophic since the MSBs are guaranteed to be transferred.
There may, however, be a slight reduction in performance
depending on the scale of the mismatch. In RJ Mode, however,
differences in word-width between the AD1871 and controller
have a catastrophic effect on signal performance as the MSBs
of each sample may be lost due to the mismatch.
DOUT
MSB–1
LSB+2
LSB+1
LSB
MSB–1
LSB+2
LSB+1
LSB
MSB
MSB–1
MSB
LRCLK
LEFT CHANNEL
RIGHT CHANNEL
BCLK
MSB
Figure 15. DSP Mode
相關(guān)PDF資料
PDF描述
1676859-4 CAP CER 0.82PF 200V 5% NP0 0805
1676859-3 CAP CER 0.68PF 200V 5% NP0 0805
1676859-2 CAP CER 0.56PF 200V 5% NP0 0805
1676859-1 CAP CER 0.47PF 200V 5% NP0 0805
1676858-4 CAP CER 0.82PF 100V 5% NP0 0805
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1871YRSZ 制造商:Analog Devices 功能描述:IC, ADC, 24BIT, 96KHZ, SSOP-28
AD1871YRSZ-REEL 功能描述:IC ADC STEREO 24BIT 96KHZ 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極
AD1876 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit 100 kSPS Sampling ADC
AD1876JN 制造商:Rochester Electronics LLC 功能描述:- Bulk
AD1877 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Supply 16-Bit Stereo ADC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*