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參數(shù)資料
| 型號： | AD5259EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5259 DGTL POT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5259 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD5259BCPZ5-R7TR-ND - IC POT DGTL 5K 256POS 10LFCSP AD5259BCPZ50-R7TR-ND - IC POT DGTL 50K 256POS 10LFCSP AD5259BCPZ10-R7TR-ND - IC POT DGTL 10K 256POS 10LFCSP AD5259BCPZ100-R7TR-ND - IC POT DGTL 100K 256POS 10LFCSP AD5259BRMZ5-ND - IC POT DGTL 5K 256POS 10-MSOP AD5259BRMZ50-ND - IC POT DGTL 50K 256POS 10-MSOP AD5259BRMZ5-R7-ND - IC POT DGTL 5K 256POS 10MSOP AD5259BRMZ100-R7-ND - IC POT DGTL 100K 256POS 10MSOP AD5259BRMZ10-R7-ND - IC POT DGTL 10K 256POS 10MSOP AD5259BRMZ50-R7-ND - IC POT DGTL 50K 256POS 10MSOP 更多... |
Data Sheet
AD5259
Rev. C | Page 19 of 24
ESD PROTECTION OF DIGITAL PINS AND
RESISTOR TERMINALS
The AD5259 VDD, VLOGIC, and GND power supplies define the
boundary conditions for proper 3-terminal and digital input
operation. Supply signals present on Terminal A, Terminal B,
and Terminal W that exceed VDD or GND are clamped by the
internal forward biased ESD protection diodes (see Figure 42).
Digital Input SCL and Digital Input SDA are clamped by ESD
protection diodes with respect to VLOGIC and GND as shown in
GND
A
W
B
VDD
05026-039
Figure 42. Maximum Terminal Voltages Set by VDD and GND
GND
SCL
SDA
VLOGIC
05026-040
Figure 43. Maximum Terminal Voltages Set by VLOGIC and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 42), it
is important to power GND/VDD/VLOGIC before applying any
voltage to Terminal A, Terminal B, and Terminal W; otherwise,
the diode is forward biased, so the VDD and VLOGIC are powered
unintentionally and may affect the user’s circuit. The ideal power-
up sequence is in the following order: GND, VDD, VLOGIC, digital
inputs, and then VA, VB, VW. The relative order of powering
VA, VB, VW, and the digital inputs is not important as long as
they are powered after GND/VDD/VLOGIC.
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to use compact, minimum lead length layout
design. The leads to the inputs should be as direct as possible
with minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic capaci-
tors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 44). The digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
VDD
GND
VDD
C2
10
F
C1
0.1
F
AD5259
+
05026-041
Figure 44. Power Supply Bypassing
MULTIPLE DEVICES ON ONE BUS
The AD5259 has two configurable address pins, Pin AD0 and
Pin AD1. The state of these two pins is registered upon power-
up and decoded into a corresponding I2C-compatible 7-bit
address (see Table 5). This allows up to four devices on the bus
to be written to or read from independently.
EVALUATION BOARD
An evaluation board, with all necessary software, is available
to program the AD5259 from any PC running Windows 98/
2000/ XP. The graphical user interface, as shown in Figure 45,
is straightforward and easy to use. More detailed information
is available in the board’s user manual.
05026-042
Figure 45. AD5259 Evaluation Board Software
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