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參數(shù)資料
| 型號： | AD5259EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD5259 DGTL POT |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5259 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD5259BCPZ5-R7TR-ND - IC POT DGTL 5K 256POS 10LFCSP AD5259BCPZ50-R7TR-ND - IC POT DGTL 50K 256POS 10LFCSP AD5259BCPZ10-R7TR-ND - IC POT DGTL 10K 256POS 10LFCSP AD5259BCPZ100-R7TR-ND - IC POT DGTL 100K 256POS 10LFCSP AD5259BRMZ5-ND - IC POT DGTL 5K 256POS 10-MSOP AD5259BRMZ50-ND - IC POT DGTL 50K 256POS 10-MSOP AD5259BRMZ5-R7-ND - IC POT DGTL 5K 256POS 10MSOP AD5259BRMZ100-R7-ND - IC POT DGTL 100K 256POS 10MSOP AD5259BRMZ10-R7-ND - IC POT DGTL 10K 256POS 10MSOP AD5259BRMZ50-R7-ND - IC POT DGTL 50K 256POS 10MSOP 更多... |
Data Sheet
AD5259
Rev. C | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05026-
002
AD5259
TOP VIEW
(Not to Scale)
W
1
AD0
2
AD1
3
SDA 4
SCL
5
A
B
VDD
GND
VLOGIC
10
9
8
7
6
NOTES
1. THE EXPOSED PAD SHOULD
BE CONNECTED TO GND OR
LEFT FLOATING.
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin
Mnemonic
Description
1
W
W Terminal, GND ≤ V
W ≤ VDD.
2
ADO
Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up.
3
AD1
Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up.
4
SDA
Serial Data Input/Output.
5
SCL
Serial Clock Input. Positive edge triggered.
6
V
LOGIC
Logic Power Supply.
7
GND
Digital Ground.
8
V
DD
Positive Power Supply.
9
B
B Terminal, GND ≤ V
B ≤ VDD.
10
A
A Terminal, GND ≤ V
A ≤ VDD.
11
EPAD
Exposed Pad. The exposed pad should be connected to GND or left floating.
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