參數(shù)資料
型號: AD5259EVAL
廠商: Analog Devices Inc
文件頁數(shù): 14/24頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD5259 DGTL POT
標準包裝: 1
主要目的: 數(shù)字電位器
已用 IC / 零件: AD5259
已供物品:
相關(guān)產(chǎn)品: AD5259BCPZ5-R7TR-ND - IC POT DGTL 5K 256POS 10LFCSP
AD5259BCPZ50-R7TR-ND - IC POT DGTL 50K 256POS 10LFCSP
AD5259BCPZ10-R7TR-ND - IC POT DGTL 10K 256POS 10LFCSP
AD5259BCPZ100-R7TR-ND - IC POT DGTL 100K 256POS 10LFCSP
AD5259BRMZ5-ND - IC POT DGTL 5K 256POS 10-MSOP
AD5259BRMZ50-ND - IC POT DGTL 50K 256POS 10-MSOP
AD5259BRMZ5-R7-ND - IC POT DGTL 5K 256POS 10MSOP
AD5259BRMZ100-R7-ND - IC POT DGTL 100K 256POS 10MSOP
AD5259BRMZ10-R7-ND - IC POT DGTL 10K 256POS 10MSOP
AD5259BRMZ50-R7-ND - IC POT DGTL 50K 256POS 10MSOP
更多...
Data Sheet
AD5259
Rev. C | Page 21 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-
A
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 48. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
TOP VIEW
10
1
6
5
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0
2-
27-
2
012
-B
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
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